[v3,09/42] intel/compiler: allow extended math functions with HF operands

Submitted by Iago Toral Quiroga on Jan. 15, 2019, 1:53 p.m.

Details

Message ID 20190115135414.2313-10-itoral@igalia.com
State New
Headers show
Series "intel: VK_KHR_shader_float16_int8 implementation" ( rev: 5 4 ) in Mesa

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Commit Message

Iago Toral Quiroga Jan. 15, 2019, 1:53 p.m.
The PRM states that half-float operands are supported since gen9.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
---
 src/intel/compiler/brw_eu_emit.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 45e2552783b..e21df4624b3 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -1874,8 +1874,10 @@  void gen6_math(struct brw_codegen *p,
       assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
              (devinfo->gen >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
    } else {
-      assert(src0.type == BRW_REGISTER_TYPE_F);
-      assert(src1.type == BRW_REGISTER_TYPE_F);
+      assert(src0.type == BRW_REGISTER_TYPE_F ||
+             (src0.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9));
+      assert(src1.type == BRW_REGISTER_TYPE_F ||
+             (src1.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9));
    }
 
    /* Source modifiers are ignored for extended math instructions on Gen6. */

Comments

This should probably be squashed into patch 7 so that it's clear from one
patch that it's being properly handed on both sides of the gen9 boundary.
I'd also squash in patch 15 and just give the whole thing the title "Handle
extended math restrictions for half-float" with a detailed message
describing what all we have to handle.  If you want to keep it as two
patches, that's fine but unnecessary.

On Tue, Jan 15, 2019 at 7:54 AM Iago Toral Quiroga <itoral@igalia.com>
wrote:

> The PRM states that half-float operands are supported since gen9.
>
> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
> ---
>  src/intel/compiler/brw_eu_emit.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/compiler/brw_eu_emit.c
> b/src/intel/compiler/brw_eu_emit.c
> index 45e2552783b..e21df4624b3 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -1874,8 +1874,10 @@ void gen6_math(struct brw_codegen *p,
>        assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
>               (devinfo->gen >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
>     } else {
> -      assert(src0.type == BRW_REGISTER_TYPE_F);
> -      assert(src1.type == BRW_REGISTER_TYPE_F);
> +      assert(src0.type == BRW_REGISTER_TYPE_F ||
> +             (src0.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9));
> +      assert(src1.type == BRW_REGISTER_TYPE_F ||
> +             (src1.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9));
>     }
>
>     /* Source modifiers are ignored for extended math instructions on
> Gen6. */
> --
> 2.17.1
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
Sure, I'll squash all 3.

On Thu, 2019-01-17 at 14:00 -0600, Jason Ekstrand wrote:
> This should probably be squashed into patch 7 so that it's clear from
> one patch that it's being properly handed on both sides of the gen9
> boundary.  I'd also squash in patch 15 and just give the whole thing
> the title "Handle extended math restrictions for half-float" with a
> detailed message describing what all we have to handle.  If you want
> to keep it as two patches, that's fine but unnecessary.
> 
> 
> On Tue, Jan 15, 2019 at 7:54 AM Iago Toral Quiroga <itoral@igalia.com
> > wrote:
> > The PRM states that half-float operands are supported since gen9.
> > 
> > 
> > 
> > Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
> > 
> > ---
> > 
> >  src/intel/compiler/brw_eu_emit.c | 6 ++++--
> > 
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > 
> > 
> > diff --git a/src/intel/compiler/brw_eu_emit.c
> > b/src/intel/compiler/brw_eu_emit.c
> > 
> > index 45e2552783b..e21df4624b3 100644
> > 
> > --- a/src/intel/compiler/brw_eu_emit.c
> > 
> > +++ b/src/intel/compiler/brw_eu_emit.c
> > 
> > @@ -1874,8 +1874,10 @@ void gen6_math(struct brw_codegen *p,
> > 
> >        assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
> > 
> >               (devinfo->gen >= 8 && src1.file ==
> > BRW_IMMEDIATE_VALUE));
> > 
> >     } else {
> > 
> > -      assert(src0.type == BRW_REGISTER_TYPE_F);
> > 
> > -      assert(src1.type == BRW_REGISTER_TYPE_F);
> > 
> > +      assert(src0.type == BRW_REGISTER_TYPE_F ||
> > 
> > +             (src0.type == BRW_REGISTER_TYPE_HF && devinfo->gen >=
> > 9));
> > 
> > +      assert(src1.type == BRW_REGISTER_TYPE_F ||
> > 
> > +             (src1.type == BRW_REGISTER_TYPE_HF && devinfo->gen >=
> > 9));
> > 
> >     }
> > 
> > 
> > 
> >     /* Source modifiers are ignored for extended math instructions
> > on Gen6. */
> >