[10/13] drm/i915: Track pipe csc enable in crtc state

Submitted by Ville Syrjala on Jan. 11, 2019, 5:08 p.m.

Details

Message ID 20190111170823.4441-11-ville.syrjala@linux.intel.com
State New
Series "Enable/disable gamma/csc dynamically and fix C8"
Headers show

Commit Message

Ville Syrjala Jan. 11, 2019, 5:08 p.m.
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Just like we did for pipe gamma, let's also track the pipe csc
state. The hardware only exists on ILK+, and currently we always
enable it on hsw+ and never on any other platforms. Just like
with pipe gamma, the primary plane control register is used
for the readout on pre-SKL, and the pipe bottom color register
on SKL+.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  4 ++--
 drivers/gpu/drm/i915/intel_color.c   |  7 ++++++-
 drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++----
 drivers/gpu/drm/i915/intel_drv.h     |  3 +++
 drivers/gpu/drm/i915/intel_sprite.c  |  6 ++++--
 5 files changed, 29 insertions(+), 9 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7f0913bc1b47..8848721dd691 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6120,7 +6120,7 @@  enum {
 #define   MCURSOR_PIPE_SELECT_SHIFT	28
 #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
-#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24)
+#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
 #define   MCURSOR_ROTATE_180	(1 << 15)
 #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
 #define _CURABASE		0x70084
@@ -6175,7 +6175,7 @@  enum {
 #define   DISPPLANE_RGBA888			(0xf << 26)
 #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
 #define   DISPPLANE_STEREO_DISABLE		0
-#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24)
+#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
 #define   DISPPLANE_SEL_PIPE_SHIFT		24
 #define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)
 #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 313b281204fa..8d7ea902a34b 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -397,7 +397,8 @@  static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 	val = 0;
 	if (crtc_state->gamma_enable)
 		val |= PIPE_BOTTOM_GAMMA_ENABLE;
-	val |= PIPE_BOTTOM_CSC_ENABLE;
+	if (crtc_state->csc_enable)
+		val |= PIPE_BOTTOM_CSC_ENABLE;
 	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
 
 	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
@@ -644,6 +645,10 @@  int intel_color_check(struct intel_crtc_state *crtc_state)
 
 	crtc_state->gamma_enable = true;
 
+	if (INTEL_GEN(dev_priv) >= 9 ||
+	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
+		crtc_state->csc_enable = true;
+
 	/*
 	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
 	 * size (256 entries).
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 896ce95790cb..2e66b398167e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3189,7 +3189,7 @@  static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		dspcntr |= DISPPLANE_GAMMA_ENABLE;
 
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+	if (crtc_state->csc_enable)
 		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
 
 	if (INTEL_GEN(dev_priv) < 5)
@@ -3668,7 +3668,8 @@  u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
 
-	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
+	if (crtc_state->csc_enable)
+		plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 
 	return plane_ctl;
 }
@@ -3723,7 +3724,8 @@  u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
 
-	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
+	if (crtc_state->csc_enable)
+		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
 
 	return plane_color_ctl;
 }
@@ -8052,6 +8054,10 @@  static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
 
 	if (tmp & DISPPLANE_GAMMA_ENABLE)
 		crtc_state->gamma_enable = true;
+
+	if (!HAS_GMCH_DISPLAY(dev_priv) &&
+	    tmp & DISPPLANE_PIPE_CSC_ENABLE)
+		crtc_state->csc_enable = true;
 }
 
 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
@@ -9812,6 +9818,9 @@  static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 
 		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
 			pipe_config->gamma_enable = true;
+
+		if (tmp & PIPE_BOTTOM_CSC_ENABLE)
+			pipe_config->csc_enable = true;
 	} else {
 		i9xx_get_pipe_color_config(pipe_config);
 	}
@@ -10144,7 +10153,7 @@  static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		cntl = MCURSOR_GAMMA_ENABLE;
 
-	if (HAS_DDI(dev_priv))
+	if (crtc_state->csc_enable)
 		cntl |= MCURSOR_PIPE_CSC_ENABLE;
 
 	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
@@ -12020,6 +12029,7 @@  intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 
 	PIPE_CONF_CHECK_X(gamma_mode);
 	PIPE_CONF_CHECK_BOOL(gamma_enable);
+	PIPE_CONF_CHECK_BOOL(csc_enable);
 
 	PIPE_CONF_CHECK_P(shared_dpll);
 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index eee734b48919..a4496f799af3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -949,6 +949,9 @@  struct intel_crtc_state {
 	/* enable pipe gamma? */
 	bool gamma_enable;
 
+	/* enable pipe csc? */
+	bool csc_enable;
+
 	/* Display Stream compression state */
 	struct {
 		bool compression_enable;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 034a355692db..1fe983f0ef51 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -917,13 +917,12 @@  vlv_plane_get_hw_state(struct intel_plane *plane,
 
 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
 	u32 sprctl = 0;
 
 	if (crtc_state->gamma_enable)
 		sprctl |= SPRITE_GAMMA_ENABLE;
 
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+	if (crtc_state->csc_enable)
 		sprctl |= SPRITE_PIPE_CSC_ENABLE;
 
 	return sprctl;
@@ -1112,6 +1111,9 @@  static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->gamma_enable)
 		dvscntr |= DVS_GAMMA_ENABLE;
 
+	if (crtc_state->csc_enable)
+		dvscntr |= DVS_PIPE_CSC_ENABLE;
+
 	return dvscntr;
 }
 

Comments

Matt Roper Jan. 16, 2019, 7:43 p.m.
On Fri, Jan 11, 2019 at 07:08:20PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Just like we did for pipe gamma, let's also track the pipe csc
> state. The hardware only exists on ILK+, and currently we always
> enable it on hsw+ and never on any other platforms. Just like
> with pipe gamma, the primary plane control register is used
> for the readout on pre-SKL, and the pipe bottom color register
> on SKL+.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  4 ++--
>  drivers/gpu/drm/i915/intel_color.c   |  7 ++++++-
>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++----
>  drivers/gpu/drm/i915/intel_drv.h     |  3 +++
>  drivers/gpu/drm/i915/intel_sprite.c  |  6 ++++--
>  5 files changed, 29 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7f0913bc1b47..8848721dd691 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6120,7 +6120,7 @@ enum {
>  #define   MCURSOR_PIPE_SELECT_SHIFT	28
>  #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
>  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
> -#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24)
> +#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
>  #define   MCURSOR_ROTATE_180	(1 << 15)
>  #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
>  #define _CURABASE		0x70084
> @@ -6175,7 +6175,7 @@ enum {
>  #define   DISPPLANE_RGBA888			(0xf << 26)
>  #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
>  #define   DISPPLANE_STEREO_DISABLE		0
> -#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24)
> +#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
>  #define   DISPPLANE_SEL_PIPE_SHIFT		24
>  #define   DISPPLANE_SEL_PIPE_MASK		(3 << DISPPLANE_SEL_PIPE_SHIFT)
>  #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 313b281204fa..8d7ea902a34b 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -397,7 +397,8 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
>  	val = 0;
>  	if (crtc_state->gamma_enable)
>  		val |= PIPE_BOTTOM_GAMMA_ENABLE;
> -	val |= PIPE_BOTTOM_CSC_ENABLE;
> +	if (crtc_state->csc_enable)
> +		val |= PIPE_BOTTOM_CSC_ENABLE;
>  	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
>  
>  	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
> @@ -644,6 +645,10 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>  
>  	crtc_state->gamma_enable = true;
>  
> +	if (INTEL_GEN(dev_priv) >= 9 ||
> +	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> +		crtc_state->csc_enable = true;
> +
>  	/*
>  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>  	 * size (256 entries).
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 896ce95790cb..2e66b398167e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3189,7 +3189,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		dspcntr |= DISPPLANE_GAMMA_ENABLE;
>  
> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +	if (crtc_state->csc_enable)
>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>  
>  	if (INTEL_GEN(dev_priv) < 5)
> @@ -3668,7 +3668,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
>  
> -	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
> +	if (crtc_state->csc_enable)
> +		plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
>  
>  	return plane_ctl;
>  }
> @@ -3723,7 +3724,8 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
>  
> -	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> +	if (crtc_state->csc_enable)
> +		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>  
>  	return plane_color_ctl;
>  }
> @@ -8052,6 +8054,10 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
>  
>  	if (tmp & DISPPLANE_GAMMA_ENABLE)
>  		crtc_state->gamma_enable = true;
> +
> +	if (!HAS_GMCH_DISPLAY(dev_priv) &&
> +	    tmp & DISPPLANE_PIPE_CSC_ENABLE)
> +		crtc_state->csc_enable = true;
>  }
>  
>  static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> @@ -9812,6 +9818,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  
>  		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
>  			pipe_config->gamma_enable = true;
> +
> +		if (tmp & PIPE_BOTTOM_CSC_ENABLE)
> +			pipe_config->csc_enable = true;
>  	} else {
>  		i9xx_get_pipe_color_config(pipe_config);
>  	}
> @@ -10144,7 +10153,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		cntl = MCURSOR_GAMMA_ENABLE;
>  
> -	if (HAS_DDI(dev_priv))
> +	if (crtc_state->csc_enable)
>  		cntl |= MCURSOR_PIPE_CSC_ENABLE;
>  
>  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> @@ -12020,6 +12029,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  
>  	PIPE_CONF_CHECK_X(gamma_mode);
>  	PIPE_CONF_CHECK_BOOL(gamma_enable);
> +	PIPE_CONF_CHECK_BOOL(csc_enable);
>  
>  	PIPE_CONF_CHECK_P(shared_dpll);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index eee734b48919..a4496f799af3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -949,6 +949,9 @@ struct intel_crtc_state {
>  	/* enable pipe gamma? */
>  	bool gamma_enable;
>  
> +	/* enable pipe csc? */
> +	bool csc_enable;
> +
>  	/* Display Stream compression state */
>  	struct {
>  		bool compression_enable;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 034a355692db..1fe983f0ef51 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -917,13 +917,12 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
>  
>  static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>  	u32 sprctl = 0;
>  
>  	if (crtc_state->gamma_enable)
>  		sprctl |= SPRITE_GAMMA_ENABLE;
>  
> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> +	if (crtc_state->csc_enable)
>  		sprctl |= SPRITE_PIPE_CSC_ENABLE;
>  
>  	return sprctl;
> @@ -1112,6 +1111,9 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->gamma_enable)
>  		dvscntr |= DVS_GAMMA_ENABLE;
>  
> +	if (crtc_state->csc_enable)
> +		dvscntr |= DVS_PIPE_CSC_ENABLE;
> +
>  	return dvscntr;
>  }
>  
> -- 
> 2.19.2
>
Shankar, Uma Jan. 17, 2019, 5:17 a.m.
>-----Original Message-----
>From: Roper, Matthew D
>Sent: Thursday, January 17, 2019 1:14 AM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
>Subject: Re: [PATCH 10/13] drm/i915: Track pipe csc enable in crtc state
>
>On Fri, Jan 11, 2019 at 07:08:20PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Just like we did for pipe gamma, let's also track the pipe csc state.
>> The hardware only exists on ILK+, and currently we always enable it on
>> hsw+ and never on any other platforms. Just like with pipe gamma, the
>> primary plane control register is used for the readout on pre-SKL, and
>> the pipe bottom color register on SKL+.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>> ---
>>  drivers/gpu/drm/i915/i915_reg.h      |  4 ++--
>>  drivers/gpu/drm/i915/intel_color.c   |  7 ++++++-
>>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++----
>>  drivers/gpu/drm/i915/intel_drv.h     |  3 +++
>>  drivers/gpu/drm/i915/intel_sprite.c  |  6 ++++--
>>  5 files changed, 29 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 7f0913bc1b47..8848721dd691
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6120,7 +6120,7 @@ enum {
>>  #define   MCURSOR_PIPE_SELECT_SHIFT	28
>>  #define   MCURSOR_PIPE_SELECT(pipe)	((pipe) << 28)
>>  #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
>> -#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24)
>> +#define   MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
>>  #define   MCURSOR_ROTATE_180	(1 << 15)
>>  #define   MCURSOR_TRICKLE_FEED_DISABLE	(1 << 14)
>>  #define _CURABASE		0x70084
>> @@ -6175,7 +6175,7 @@ enum {
>>  #define   DISPPLANE_RGBA888			(0xf << 26)
>>  #define   DISPPLANE_STEREO_ENABLE		(1 << 25)
>>  #define   DISPPLANE_STEREO_DISABLE		0
>> -#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24)
>> +#define   DISPPLANE_PIPE_CSC_ENABLE		(1 << 24) /* ilk+ */
>>  #define   DISPPLANE_SEL_PIPE_SHIFT		24
>>  #define   DISPPLANE_SEL_PIPE_MASK		(3 <<
>DISPPLANE_SEL_PIPE_SHIFT)
>>  #define   DISPPLANE_SEL_PIPE(pipe)		((pipe) <<
>DISPPLANE_SEL_PIPE_SHIFT)
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 313b281204fa..8d7ea902a34b 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -397,7 +397,8 @@ static void skl_color_commit(const struct
>intel_crtc_state *crtc_state)
>>  	val = 0;
>>  	if (crtc_state->gamma_enable)
>>  		val |= PIPE_BOTTOM_GAMMA_ENABLE;
>> -	val |= PIPE_BOTTOM_CSC_ENABLE;
>> +	if (crtc_state->csc_enable)
>> +		val |= PIPE_BOTTOM_CSC_ENABLE;
>>  	I915_WRITE(PIPE_BOTTOM_COLOR(pipe), val);
>>
>>  	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>@@
>> -644,6 +645,10 @@ int intel_color_check(struct intel_crtc_state
>> *crtc_state)
>>
>>  	crtc_state->gamma_enable = true;
>>
>> +	if (INTEL_GEN(dev_priv) >= 9 ||
>> +	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>> +		crtc_state->csc_enable = true;
>> +
>>  	/*
>>  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>>  	 * size (256 entries).
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 896ce95790cb..2e66b398167e 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -3189,7 +3189,7 @@ static u32 i9xx_plane_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		dspcntr |= DISPPLANE_GAMMA_ENABLE;
>>
>> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> +	if (crtc_state->csc_enable)
>>  		dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>>
>>  	if (INTEL_GEN(dev_priv) < 5)
>> @@ -3668,7 +3668,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state
>*crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
>>
>> -	plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
>> +	if (crtc_state->csc_enable)
>> +		plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
>>
>>  	return plane_ctl;
>>  }
>> @@ -3723,7 +3724,8 @@ u32 glk_plane_color_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
>>
>> -	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>> +	if (crtc_state->csc_enable)
>> +		plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
>>
>>  	return plane_color_ctl;
>>  }
>> @@ -8052,6 +8054,10 @@ static void i9xx_get_pipe_color_config(struct
>> intel_crtc_state *crtc_state)
>>
>>  	if (tmp & DISPPLANE_GAMMA_ENABLE)
>>  		crtc_state->gamma_enable = true;
>> +
>> +	if (!HAS_GMCH_DISPLAY(dev_priv) &&
>> +	    tmp & DISPPLANE_PIPE_CSC_ENABLE)
>> +		crtc_state->csc_enable = true;
>>  }
>>
>>  static bool i9xx_get_pipe_config(struct intel_crtc *crtc, @@ -9812,6
>> +9818,9 @@ static bool haswell_get_pipe_config(struct intel_crtc
>> *crtc,
>>
>>  		if (tmp & PIPE_BOTTOM_GAMMA_ENABLE)
>>  			pipe_config->gamma_enable = true;
>> +
>> +		if (tmp & PIPE_BOTTOM_CSC_ENABLE)
>> +			pipe_config->csc_enable = true;
>>  	} else {
>>  		i9xx_get_pipe_color_config(pipe_config);
>>  	}
>> @@ -10144,7 +10153,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		cntl = MCURSOR_GAMMA_ENABLE;
>>
>> -	if (HAS_DDI(dev_priv))
>> +	if (crtc_state->csc_enable)
>>  		cntl |= MCURSOR_PIPE_CSC_ENABLE;
>>
>>  	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) @@ -12020,6
>> +12029,7 @@ intel_pipe_config_compare(struct drm_i915_private
>> *dev_priv,
>>
>>  	PIPE_CONF_CHECK_X(gamma_mode);
>>  	PIPE_CONF_CHECK_BOOL(gamma_enable);
>> +	PIPE_CONF_CHECK_BOOL(csc_enable);
>>
>>  	PIPE_CONF_CHECK_P(shared_dpll);
>>  	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index eee734b48919..a4496f799af3 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -949,6 +949,9 @@ struct intel_crtc_state {
>>  	/* enable pipe gamma? */
>>  	bool gamma_enable;
>>
>> +	/* enable pipe csc? */
>> +	bool csc_enable;
>> +
>>  	/* Display Stream compression state */
>>  	struct {
>>  		bool compression_enable;
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index 034a355692db..1fe983f0ef51 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -917,13 +917,12 @@ vlv_plane_get_hw_state(struct intel_plane
>> *plane,
>>
>>  static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state
>> *crtc_state)  {
>> -	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>>  	u32 sprctl = 0;
>>
>>  	if (crtc_state->gamma_enable)
>>  		sprctl |= SPRITE_GAMMA_ENABLE;
>>
>> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>> +	if (crtc_state->csc_enable)
>>  		sprctl |= SPRITE_PIPE_CSC_ENABLE;
>>
>>  	return sprctl;
>> @@ -1112,6 +1111,9 @@ static u32 g4x_sprite_ctl_crtc(const struct
>intel_crtc_state *crtc_state)
>>  	if (crtc_state->gamma_enable)
>>  		dvscntr |= DVS_GAMMA_ENABLE;
>>
>> +	if (crtc_state->csc_enable)
>> +		dvscntr |= DVS_PIPE_CSC_ENABLE;
>> +
>>  	return dvscntr;
>>  }
>>
>> --
>> 2.19.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795