[05/13] drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()

Submitted by Ville Syrjala on Jan. 11, 2019, 5:08 p.m.

Details

Message ID 20190111170823.4441-6-ville.syrjala@linux.intel.com
State New
Series "Enable/disable gamma/csc dynamically and fix C8"
Headers show

Commit Message

Ville Syrjala Jan. 11, 2019, 5:08 p.m.
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For bdw+ let's move the GAMMA_MODE write for the legacy LUT
mode into the .load_luts() funciton directly, rather than
relying on haswell_load_luts(). We'll be getting rid of
haswell_load_luts() entirely soon, and it's anyway cleaner
to have the GAMMA_MODE write in a single place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 36 +++++++++++++++++-------------
 1 file changed, 20 insertions(+), 16 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 0dfd104b89d7..df3567686c45 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -473,21 +473,20 @@  static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 
 	if (crtc_state_is_legacy_gamma(crtc_state)) {
-		haswell_load_luts(crtc_state);
-		return;
-	}
+		i9xx_load_luts(crtc_state);
+	} else {
+		bdw_load_degamma_lut(crtc_state);
+		bdw_load_gamma_lut(crtc_state,
+				   INTEL_INFO(dev_priv)->color.degamma_lut_size);
 
-	bdw_load_degamma_lut(crtc_state);
-	bdw_load_gamma_lut(crtc_state,
-			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
+		/*
+		 * Reset the index, otherwise it prevents the legacy palette to be
+		 * written properly.
+		 */
+		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+	}
 
 	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
-
-	/*
-	 * Reset the index, otherwise it prevents the legacy palette to be
-	 * written properly.
-	 */
-	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 }
 
 static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
@@ -530,11 +529,16 @@  static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 	glk_load_degamma_lut(crtc_state);
 
 	if (crtc_state_is_legacy_gamma(crtc_state)) {
-		haswell_load_luts(crtc_state);
-		return;
-	}
+		i9xx_load_luts(crtc_state);
+	} else {
+		bdw_load_gamma_lut(crtc_state, 0);
 
-	bdw_load_gamma_lut(crtc_state, 0);
+		/*
+		 * Reset the index, otherwise it prevents the legacy palette to be
+		 * written properly.
+		 */
+		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
+	}
 
 	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
 }

Comments

Matt Roper Jan. 12, 2019, 12:57 a.m.
On Fri, Jan 11, 2019 at 07:08:15PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> For bdw+ let's move the GAMMA_MODE write for the legacy LUT
> mode into the .load_luts() funciton directly, rather than
> relying on haswell_load_luts(). We'll be getting rid of
> haswell_load_luts() entirely soon, and it's anyway cleaner
> to have the GAMMA_MODE write in a single place.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_color.c | 36 +++++++++++++++++-------------
>  1 file changed, 20 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 0dfd104b89d7..df3567686c45 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -473,21 +473,20 @@ static void broadwell_load_luts(const struct intel_crtc_state *crtc_state)
>  	enum pipe pipe = crtc->pipe;
>  
>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
> -		haswell_load_luts(crtc_state);
> -		return;
> -	}
> +		i9xx_load_luts(crtc_state);
> +	} else {
> +		bdw_load_degamma_lut(crtc_state);
> +		bdw_load_gamma_lut(crtc_state,
> +				   INTEL_INFO(dev_priv)->color.degamma_lut_size);
>  
> -	bdw_load_degamma_lut(crtc_state);
> -	bdw_load_gamma_lut(crtc_state,
> -			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
> +		/*
> +		 * Reset the index, otherwise it prevents the legacy palette to be
> +		 * written properly.
> +		 */
> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> +	}
>  
>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
> -
> -	/*
> -	 * Reset the index, otherwise it prevents the legacy palette to be
> -	 * written properly.
> -	 */
> -	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>  }
>  
>  static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
> @@ -530,11 +529,16 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
>  	glk_load_degamma_lut(crtc_state);
>  
>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
> -		haswell_load_luts(crtc_state);
> -		return;
> -	}
> +		i9xx_load_luts(crtc_state);
> +	} else {
> +		bdw_load_gamma_lut(crtc_state, 0);
>  
> -	bdw_load_gamma_lut(crtc_state, 0);
> +		/*
> +		 * Reset the index, otherwise it prevents the legacy palette to be
> +		 * written properly.
> +		 */
> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> +	}
>  
>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>  }
> -- 
> 2.19.2
>
Shankar, Uma Jan. 16, 2019, 5:26 p.m.
>-----Original Message-----
>From: Roper, Matthew D
>Sent: Saturday, January 12, 2019 6:27 AM
>To: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>
>Subject: Re: [PATCH 05/13] drm/i915: Pull GAMMA_MODE write out from
>haswell_load_luts()
>
>On Fri, Jan 11, 2019 at 07:08:15PM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> For bdw+ let's move the GAMMA_MODE write for the legacy LUT mode into
>> the .load_luts() funciton directly, rather than relying on
>> haswell_load_luts(). We'll be getting rid of
>> haswell_load_luts() entirely soon, and it's anyway cleaner to have the
>> GAMMA_MODE write in a single place.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>> ---
>>  drivers/gpu/drm/i915/intel_color.c | 36
>> +++++++++++++++++-------------
>>  1 file changed, 20 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 0dfd104b89d7..df3567686c45 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -473,21 +473,20 @@ static void broadwell_load_luts(const struct
>intel_crtc_state *crtc_state)
>>  	enum pipe pipe = crtc->pipe;
>>
>>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
>> -		haswell_load_luts(crtc_state);
>> -		return;
>> -	}
>> +		i9xx_load_luts(crtc_state);
>> +	} else {
>> +		bdw_load_degamma_lut(crtc_state);
>> +		bdw_load_gamma_lut(crtc_state,
>> +				   INTEL_INFO(dev_priv)-
>>color.degamma_lut_size);
>>
>> -	bdw_load_degamma_lut(crtc_state);
>> -	bdw_load_gamma_lut(crtc_state,
>> -			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
>> +		/*
>> +		 * Reset the index, otherwise it prevents the legacy palette to be
>> +		 * written properly.
>> +		 */
>> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>> +	}
>>
>>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);
>> -
>> -	/*
>> -	 * Reset the index, otherwise it prevents the legacy palette to be
>> -	 * written properly.
>> -	 */
>> -	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>>  }
>>
>>  static void glk_load_degamma_lut(const struct intel_crtc_state
>> *crtc_state) @@ -530,11 +529,16 @@ static void glk_load_luts(const struct
>intel_crtc_state *crtc_state)
>>  	glk_load_degamma_lut(crtc_state);
>>
>>  	if (crtc_state_is_legacy_gamma(crtc_state)) {
>> -		haswell_load_luts(crtc_state);
>> -		return;
>> -	}
>> +		i9xx_load_luts(crtc_state);
>> +	} else {
>> +		bdw_load_gamma_lut(crtc_state, 0);
>>
>> -	bdw_load_gamma_lut(crtc_state, 0);
>> +		/*
>> +		 * Reset the index, otherwise it prevents the legacy palette to be
>> +		 * written properly.
>> +		 */
>> +		I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>> +	}
>>
>>  	I915_WRITE(GAMMA_MODE(pipe), crtc_state->gamma_mode);  }
>> --
>> 2.19.2
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795