[1/2] drm/amdgpu: Add NBIO SMN headers v2

Submitted by Deucher, Alexander on Jan. 9, 2019, 3:05 p.m.

Details

Message ID BN6PR12MB180933A994DA3151BD165801F78B0@BN6PR12MB1809.namprd12.prod.outlook.com
State New
Headers show
Series "Series without cover letter" ( rev: 2 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Deucher, Alexander Jan. 9, 2019, 3:05 p.m.
Series is:

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

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diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index accdedd..1965756 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -27,13 +27,9 @@ 
 #include "nbio/nbio_6_1_default.h"
 #include "nbio/nbio_6_1_offset.h"
 #include "nbio/nbio_6_1_sh_mask.h"
+#include "nbio/nbio_6_1_smn.h"
 #include "vega10_enum.h"

-#define smnCPM_CONTROL                                                                                  0x11180460
-#define smnPCIE_CNTL2                                                                                   0x11180070
-#define smnPCIE_CONFIG_CNTL                                                                             0x11180044
-#define smnPCIE_CI_CNTL                                                                                 0x11180080
-
 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index df34dc7..38291c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -27,13 +27,11 @@ 
 #include "nbio/nbio_7_0_default.h"
 #include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
+#include "nbio/nbio_7_0_smn.h"
 #include "vega10_enum.h"

 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c

-#define smnCPM_CONTROL                                                                                  0x11180460
-#define smnPCIE_CNTL2                                                                                   0x11180070
-
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 4cd31a2..0a61309 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -26,13 +26,10 @@ 

 #include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_7_4_0_smn.h"

 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c

-#define smnCPM_CONTROL                                                                                  0x11180460
-#define smnPCIE_CNTL2                                                                                   0x11180070
-#define smnPCIE_CI_CNTL                                                                                 0x11180080
-
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
     u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
new file mode 100644
index 0000000..8c75669
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
@@ -0,0 +1,58 @@ 
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _nbio_6_1_SMN_HEADER
+#define _nbio_6_1_SMN_HEADER
+
+
+#define smnCPM_CONTROL                                 0x11180460
+#define smnPCIE_CNTL2                                  0x11180070
+#define smnPCIE_CONFIG_CNTL                            0x11180044
+#define smnPCIE_CI_CNTL                                        0x11180080
+
+
+#define smnPCIE_PERF_COUNT_CNTL                                0x11180200
+#define smnPCIE_PERF_CNTL_TXCLK                                0x11180204
+#define smnPCIE_PERF_COUNT0_TXCLK                      0x11180208
+#define smnPCIE_PERF_COUNT1_TXCLK                      0x1118020c
+#define smnPCIE_PERF_CNTL_MST_R_CLK                    0x11180210
+#define smnPCIE_PERF_COUNT0_MST_R_CLK                  0x11180214
+#define smnPCIE_PERF_COUNT1_MST_R_CLK                  0x11180218
+#define smnPCIE_PERF_CNTL_MST_C_CLK                    0x1118021c
+#define smnPCIE_PERF_COUNT0_MST_C_CLK                  0x11180220
+#define smnPCIE_PERF_COUNT1_MST_C_CLK                  0x11180224
+#define smnPCIE_PERF_CNTL_SLV_R_CLK                    0x11180228
+#define smnPCIE_PERF_COUNT0_SLV_R_CLK                  0x1118022c
+#define smnPCIE_PERF_COUNT1_SLV_R_CLK                  0x11180230
+#define smnPCIE_PERF_CNTL_SLV_S_C_CLK                  0x11180234
+#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK                        0x11180238
+#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK                        0x1118023c
+#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK                 0x11180240
+#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK               0x11180244
+#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK               0x11180248
+#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL              0x1118024c
+#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL              0x11180250
+#define smnPCIE_PERF_CNTL_TXCLK2                       0x11180254
+#define smnPCIE_PERF_COUNT0_TXCLK2                     0x11180258
+#define smnPCIE_PERF_COUNT1_TXCLK2                     0x1118025c
+
+#endif // _nbio_6_1_SMN_HEADER
+
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
new file mode 100644
index 0000000..5563f07
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
@@ -0,0 +1,54 @@ 
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _nbio_7_0_SMN_HEADER
+#define _nbio_7_0_SMN_HEADER
+
+
+#define smnCPM_CONTROL                                 0x11180460
+#define smnPCIE_CNTL2                                  0x11180070
+
+#define smnPCIE_PERF_COUNT_CNTL                                0x11180200
+#define smnPCIE_PERF_CNTL_TXCLK                                0x11180204
+#define smnPCIE_PERF_COUNT0_TXCLK                      0x11180208
+#define smnPCIE_PERF_COUNT1_TXCLK                      0x1118020c
+#define smnPCIE_PERF_CNTL_MST_R_CLK                    0x11180210
+#define smnPCIE_PERF_COUNT0_MST_R_CLK                  0x11180214
+#define smnPCIE_PERF_COUNT1_MST_R_CLK                  0x11180218
+#define smnPCIE_PERF_CNTL_MST_C_CLK                    0x1118021c
+#define smnPCIE_PERF_COUNT0_MST_C_CLK                  0x11180220
+#define smnPCIE_PERF_COUNT1_MST_C_CLK                  0x11180224
+#define smnPCIE_PERF_CNTL_SLV_R_CLK                    0x11180228
+#define smnPCIE_PERF_COUNT0_SLV_R_CLK                  0x1118022c
+#define smnPCIE_PERF_COUNT1_SLV_R_CLK                  0x11180230
+#define smnPCIE_PERF_CNTL_SLV_S_C_CLK                  0x11180234
+#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK                        0x11180238
+#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK                        0x1118023c
+#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK                 0x11180240
+#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK               0x11180244
+#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK               0x11180248
+#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL              0x1118024c
+#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL              0x11180250
+#define smnPCIE_PERF_CNTL_TXCLK2                       0x11180254
+#define smnPCIE_PERF_COUNT0_TXCLK2                     0x11180258
+#define smnPCIE_PERF_COUNT1_TXCLK2                     0x1118025c
+
+#endif // _nbio_7_0_SMN_HEADER
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
new file mode 100644
index 0000000..c1457d8
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
@@ -0,0 +1,53 @@ 
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _nbio_7_4_0_SMN_HEADER
+#define _nbio_7_4_0_SMN_HEADER
+
+
+#define smnNBIF_MGCG_CTRL_LCLK                         0x1013a21c
+#define smnCPM_CONTROL                                 0x11180460
+#define smnPCIE_CNTL2                                  0x11180070
+#define smnPCIE_CI_CNTL                                        0x11180080
+
+#define smnPCIE_PERF_COUNT_CNTL                                0x11180200
+#define smnPCIE_PERF_CNTL_TXCLK1                       0x11180204
+#define smnPCIE_PERF_COUNT0_TXCLK1                     0x11180208
+#define smnPCIE_PERF_COUNT1_TXCLK1                     0x1118020c
+#define smnPCIE_PERF_CNTL_TXCLK2                       0x11180210
+#define smnPCIE_PERF_COUNT0_TXCLK2                     0x11180214
+#define smnPCIE_PERF_COUNT1_TXCLK2                     0x11180218
+#define smnPCIE_PERF_CNTL_TXCLK3                       0x1118021c
+#define smnPCIE_PERF_COUNT0_TXCLK3                     0x11180220
+#define smnPCIE_PERF_COUNT1_TXCLK3                     0x11180224
+#define smnPCIE_PERF_CNTL_TXCLK4                       0x11180228
+#define smnPCIE_PERF_COUNT0_TXCLK4                     0x1118022c
+#define smnPCIE_PERF_COUNT1_TXCLK4                     0x11180230
+#define smnPCIE_PERF_CNTL_SCLK1                                0x11180234
+#define smnPCIE_PERF_COUNT0_SCLK1                      0x11180238
+#define smnPCIE_PERF_COUNT1_SCLK1                      0x1118023c
+#define smnPCIE_PERF_CNTL_SCLK2                                0x11180240
+#define smnPCIE_PERF_COUNT0_SCLK2                      0x11180244
+#define smnPCIE_PERF_COUNT1_SCLK2                      0x11180248
+#define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL            0x1118024c
+#define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL            0x11180250
+
+#endif // _nbio_7_4_0_SMN_HEADER