[v1,5/5] drm/i915/gvt: Refine port select logic for CFL platform

Submitted by fred gao on Jan. 3, 2019, 7:05 p.m.

Details

Message ID 20190103190530.14170-1-fred.gao@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GVT devel

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Commit Message

fred gao Jan. 3, 2019, 7:05 p.m.
Refine the code since the port select definition for CFL is different
than SKL/BXT.

Signed-off-by: fred gao <fred.gao@intel.com>
---
 drivers/gpu/drm/i915/gvt/edid.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 752aa0fd1cc9..689961d1ce3a 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -77,6 +77,22 @@  static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
 	return chr;
 }
 
+static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
+{
+	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
+	int port = -EINVAL;
+
+	if (port_select == GMBUS_PIN_1_BXT)
+		port = PORT_B;
+	else if (port_select == GMBUS_PIN_2_BXT)
+		port = PORT_C;
+	else if (port_select == GMBUS_PIN_3_BXT)
+		port = PORT_D;
+	else if (port_select == GMBUS_PIN_4_CNP)
+		port = PORT_E;
+	return port;
+}
+
 static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
 {
 	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
@@ -133,6 +149,8 @@  static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
 
 	if (IS_BROXTON(dev_priv))
 		port = bxt_get_port_from_gmbus0(pin_select);
+	else if (HAS_PCH_CNP(dev_priv))
+		port = cnp_get_port_from_gmbus0(pin_select);
 	else
 		port = get_port_from_gmbus0(pin_select);
 	if (WARN_ON(port < 0))

Comments

On 2019.01.04 03:05:30 +0800, fred gao wrote:
> Refine the code since the port select definition for CFL is different
> than SKL/BXT.
> 
> Signed-off-by: fred gao <fred.gao@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/edid.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
> index 752aa0fd1cc9..689961d1ce3a 100644
> --- a/drivers/gpu/drm/i915/gvt/edid.c
> +++ b/drivers/gpu/drm/i915/gvt/edid.c
> @@ -77,6 +77,22 @@ static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
>  	return chr;
>  }
>  
> +static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
> +{
> +	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
> +	int port = -EINVAL;
> +
> +	if (port_select == GMBUS_PIN_1_BXT)
> +		port = PORT_B;
> +	else if (port_select == GMBUS_PIN_2_BXT)
> +		port = PORT_C;
> +	else if (port_select == GMBUS_PIN_3_BXT)
> +		port = PORT_D;
> +	else if (port_select == GMBUS_PIN_4_CNP)
> +		port = PORT_E;
> +	return port;
> +}
> +
>  static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
>  {
>  	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
> @@ -133,6 +149,8 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
>  
>  	if (IS_BROXTON(dev_priv))
>  		port = bxt_get_port_from_gmbus0(pin_select);
> +	else if (HAS_PCH_CNP(dev_priv))
> +		port = cnp_get_port_from_gmbus0(pin_select);
>  	else
>  		port = get_port_from_gmbus0(pin_select);
>  	if (WARN_ON(port < 0))

I think we need more explanation here, is PCH_CNP the only
possible PCH for CFL? Or this is just to say for CNP we should
do like that?

I don't know why we would still adjust something according
with hw config for our virtual display, maybe there's still
places to take wrong assumption...