[2/2] drm/i915: Use intel_ types more consistently for color management code

Submitted by Matt Roper on Dec. 7, 2018, 12:54 a.m.

Details

Message ID 20181207005401.13988-3-matthew.d.roper@intel.com
State New
Series "Use intel_* types more consistently"
Headers show

Commit Message

Matt Roper Dec. 7, 2018, 12:54 a.m.
Try to be more consistent about intel_* types rather than drm_* types
for lower-level driver functions.  While we're at it, let's also be more
consistent with state variable naming (half of the platforms use the
name 'state' whereas the other half used 'crtc_state').

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |   4 +-
 drivers/gpu/drm/i915/intel_color.c   | 207 ++++++++++++++++-------------------
 drivers/gpu/drm/i915/intel_display.c |  20 ++--
 drivers/gpu/drm/i915/intel_drv.h     |   8 +-
 4 files changed, 112 insertions(+), 127 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7469a7785253..48fb5e9bd08b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -321,8 +321,8 @@  struct drm_i915_display_funcs {
 	/* display clock increase/decrease */
 	/* pll clock increase/decrease */
 
-	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
-	void (*load_luts)(struct drm_crtc_state *crtc_state);
+	void (*load_csc_matrix)(struct intel_crtc_state *state);
+	void (*load_luts)(struct intel_crtc_state *state);
 };
 
 #define CSR_VERSION(major, minor)	((major) << 16 | (minor))
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 5127da286a2b..335c4702fcfb 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -74,12 +74,12 @@ 
 #define ILK_CSC_COEFF_1_0		\
 	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
 
-static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state)
+static bool crtc_state_is_legacy_gamma(struct intel_crtc_state *state)
 {
-	return !state->degamma_lut &&
-		!state->ctm &&
-		state->gamma_lut &&
-		drm_color_lut_size(state->gamma_lut) == LEGACY_LUT_LENGTH;
+	return !state->base.degamma_lut &&
+		!state->base.ctm &&
+		state->base.gamma_lut &&
+		drm_color_lut_size(state->base.gamma_lut) == LEGACY_LUT_LENGTH;
 }
 
 /*
@@ -108,10 +108,10 @@  static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
 	return result;
 }
 
-static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
+static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
 {
-	int pipe = intel_crtc->pipe;
-	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+	int pipe = crtc->pipe;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
 	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
 	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
@@ -132,14 +132,12 @@  static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
 	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
 }
 
-static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
+static void ilk_load_csc_matrix(struct intel_crtc_state *state)
 {
-	struct drm_crtc *crtc = crtc_state->crtc;
-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	int i, pipe = intel_crtc->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	int i, pipe = crtc->pipe;
 	uint16_t coeffs[9] = { 0, };
-	struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
 	bool limited_color_range = false;
 
 	/*
@@ -147,14 +145,14 @@  static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
 	 * do the range compression using the gamma LUT instead.
 	 */
 	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
-		limited_color_range = intel_crtc_state->limited_color_range;
+		limited_color_range = state->limited_color_range;
 
-	if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
-	    intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
-		ilk_load_ycbcr_conversion_matrix(intel_crtc);
+	if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+	    state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
+		ilk_load_ycbcr_conversion_matrix(crtc);
 		return;
-	} else if (crtc_state->ctm) {
-		struct drm_color_ctm *ctm = crtc_state->ctm->data;
+	} else if (state->base.ctm) {
+		struct drm_color_ctm *ctm = state->base.ctm->data;
 		const u64 *input;
 		u64 temp[9];
 
@@ -253,16 +251,15 @@  static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
 /*
  * Set up the pipe CSC unit on CherryView.
  */
-static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
+static void cherryview_load_csc_matrix(struct intel_crtc_state *state)
 {
-	struct drm_crtc *crtc = state->crtc;
-	struct drm_device *dev = crtc->dev;
+	struct drm_device *dev = state->base.crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	int pipe = to_intel_crtc(crtc)->pipe;
+	int pipe = to_intel_crtc(state->base.crtc)->pipe;
 	uint32_t mode;
 
-	if (state->ctm) {
-		struct drm_color_ctm *ctm = state->ctm->data;
+	if (state->base.ctm) {
+		struct drm_color_ctm *ctm = state->base.ctm->data;
 		uint16_t coeffs[9] = { 0, };
 		int i;
 
@@ -293,36 +290,34 @@  static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
 		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 	}
 
-	mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
+	mode = (state->base.ctm ? CGM_PIPE_MODE_CSC : 0);
 	if (!crtc_state_is_legacy_gamma(state)) {
-		mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
-			(state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
+		mode |= (state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
+			(state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
 	}
 	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
 }
 
-void intel_color_set_csc(struct drm_crtc_state *crtc_state)
+void intel_color_set_csc(struct intel_crtc_state *state)
 {
-	struct drm_device *dev = crtc_state->crtc->dev;
+	struct drm_device *dev = state->base.crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
 	if (dev_priv->display.load_csc_matrix)
-		dev_priv->display.load_csc_matrix(crtc_state);
+		dev_priv->display.load_csc_matrix(state);
 }
 
 /* Loads the legacy palette/gamma unit for the CRTC. */
-static void i9xx_load_luts_internal(struct drm_crtc *crtc,
-				    struct drm_property_blob *blob,
-				    struct intel_crtc_state *crtc_state)
+static void i9xx_load_luts_internal(struct intel_crtc_state *state,
+				    struct drm_property_blob *blob)
 {
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	enum pipe pipe = intel_crtc->pipe;
+	struct intel_crtc *crtc = to_intel_crtc(state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
 	int i;
 
 	if (HAS_GMCH_DISPLAY(dev_priv)) {
-		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		if (intel_crtc_has_type(state, INTEL_OUTPUT_DSI))
 			assert_dsi_pll_enabled(dev_priv);
 		else
 			assert_pll_enabled(dev_priv, pipe);
@@ -353,53 +348,48 @@  static void i9xx_load_luts_internal(struct drm_crtc *crtc,
 	}
 }
 
-static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
+static void i9xx_load_luts(struct intel_crtc_state *state)
 {
-	i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
-				to_intel_crtc_state(crtc_state));
+	i9xx_load_luts_internal(state, state->base.gamma_lut);
 }
 
 /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
-static void haswell_load_luts(struct drm_crtc_state *crtc_state)
+static void haswell_load_luts(struct intel_crtc_state *state)
 {
-	struct drm_crtc *crtc = crtc_state->crtc;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct intel_crtc_state *intel_crtc_state =
-		to_intel_crtc_state(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	bool reenable_ips = false;
 
 	/*
 	 * Workaround : Do not read or write the pipe palette/gamma data while
 	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 	 */
-	if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
-	    (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
-		hsw_disable_ips(intel_crtc_state);
+	if (IS_HASWELL(dev_priv) && state->ips_enabled &&
+	    (state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
+		hsw_disable_ips(state);
 		reenable_ips = true;
 	}
 
-	intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
-	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
+	state->gamma_mode = GAMMA_MODE_MODE_8BIT;
+	I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
 
-	i9xx_load_luts(crtc_state);
+	i9xx_load_luts(state);
 
 	if (reenable_ips)
-		hsw_enable_ips(intel_crtc_state);
+		hsw_enable_ips(state);
 }
 
-static void bdw_load_degamma_lut(struct drm_crtc_state *state)
+static void bdw_load_degamma_lut(struct intel_crtc_state *state)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
-	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
+	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
+	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
 	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 
 	I915_WRITE(PREC_PAL_INDEX(pipe),
 		   PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
 
-	if (state->degamma_lut) {
-		struct drm_color_lut *lut = state->degamma_lut->data;
+	if (state->base.degamma_lut) {
+		struct drm_color_lut *lut = state->base.degamma_lut->data;
 
 		for (i = 0; i < lut_size; i++) {
 			uint32_t word =
@@ -419,10 +409,10 @@  static void bdw_load_degamma_lut(struct drm_crtc_state *state)
 	}
 }
 
-static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
+static void bdw_load_gamma_lut(struct intel_crtc_state *state, u32 offset)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
-	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
+	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
+	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
 	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 
 	WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
@@ -432,8 +422,8 @@  static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
 		   PAL_PREC_AUTO_INCREMENT |
 		   offset);
 
-	if (state->gamma_lut) {
-		struct drm_color_lut *lut = state->gamma_lut->data;
+	if (state->base.gamma_lut) {
+		struct drm_color_lut *lut = state->base.gamma_lut->data;
 
 		for (i = 0; i < lut_size; i++) {
 			uint32_t word =
@@ -467,11 +457,10 @@  static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
 }
 
 /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
-static void broadwell_load_luts(struct drm_crtc_state *state)
+static void broadwell_load_luts(struct intel_crtc_state *state)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
-	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
-	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
+	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
+	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
 
 	if (crtc_state_is_legacy_gamma(state)) {
 		haswell_load_luts(state);
@@ -479,10 +468,9 @@  static void broadwell_load_luts(struct drm_crtc_state *state)
 	}
 
 	bdw_load_degamma_lut(state);
-	bdw_load_gamma_lut(state,
-			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
+	bdw_load_gamma_lut(state, INTEL_INFO(dev_priv)->color.degamma_lut_size);
 
-	intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
+	state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
 	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
 	POSTING_READ(GAMMA_MODE(pipe));
 
@@ -493,10 +481,10 @@  static void broadwell_load_luts(struct drm_crtc_state *state)
 	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
 }
 
-static void glk_load_degamma_lut(struct drm_crtc_state *state)
+static void glk_load_degamma_lut(struct intel_crtc_state *state)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
-	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
+	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
+	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
 	const uint32_t lut_size = 33;
 	uint32_t i;
 
@@ -523,13 +511,11 @@  static void glk_load_degamma_lut(struct drm_crtc_state *state)
 		I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
 }
 
-static void glk_load_luts(struct drm_crtc_state *state)
+static void glk_load_luts(struct intel_crtc_state *state)
 {
-	struct drm_crtc *crtc = state->crtc;
-	struct drm_device *dev = crtc->dev;
+	struct drm_device *dev = state->base.crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
 
 	glk_load_degamma_lut(state);
 
@@ -540,15 +526,15 @@  static void glk_load_luts(struct drm_crtc_state *state)
 
 	bdw_load_gamma_lut(state, 0);
 
-	intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
+	state->gamma_mode = GAMMA_MODE_MODE_10BIT;
 	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
 	POSTING_READ(GAMMA_MODE(pipe));
 }
 
 /* Loads the palette/gamma unit for the CRTC on CherryView. */
-static void cherryview_load_luts(struct drm_crtc_state *state)
+static void cherryview_load_luts(struct intel_crtc_state *state)
 {
-	struct drm_crtc *crtc = state->crtc;
+	struct drm_crtc *crtc = state->base.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
 	struct drm_color_lut *lut;
@@ -558,14 +544,13 @@  static void cherryview_load_luts(struct drm_crtc_state *state)
 	if (crtc_state_is_legacy_gamma(state)) {
 		/* Turn off degamma/gamma on CGM block. */
 		I915_WRITE(CGM_PIPE_MODE(pipe),
-			   (state->ctm ? CGM_PIPE_MODE_CSC : 0));
-		i9xx_load_luts_internal(crtc, state->gamma_lut,
-					to_intel_crtc_state(state));
+			   (state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
+		i9xx_load_luts_internal(state, state->base.gamma_lut);
 		return;
 	}
 
-	if (state->degamma_lut) {
-		lut = state->degamma_lut->data;
+	if (state->base.degamma_lut) {
+		lut = state->base.degamma_lut->data;
 		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 		for (i = 0; i < lut_size; i++) {
 			/* Write LUT in U0.14 format. */
@@ -579,8 +564,8 @@  static void cherryview_load_luts(struct drm_crtc_state *state)
 		}
 	}
 
-	if (state->gamma_lut) {
-		lut = state->gamma_lut->data;
+	if (state->base.gamma_lut) {
+		lut = state->base.gamma_lut->data;
 		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 		for (i = 0; i < lut_size; i++) {
 			/* Write LUT in U0.10 format. */
@@ -595,29 +580,29 @@  static void cherryview_load_luts(struct drm_crtc_state *state)
 	}
 
 	I915_WRITE(CGM_PIPE_MODE(pipe),
-		   (state->ctm ? CGM_PIPE_MODE_CSC : 0) |
-		   (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
-		   (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
+		   (state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
+		   (state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
+		   (state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
 
 	/*
 	 * Also program a linear LUT in the legacy block (behind the
 	 * CGM block).
 	 */
-	i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
+	i9xx_load_luts_internal(state, NULL);
 }
 
-void intel_color_load_luts(struct drm_crtc_state *crtc_state)
+void intel_color_load_luts(struct intel_crtc_state *state)
 {
-	struct drm_device *dev = crtc_state->crtc->dev;
+	struct drm_device *dev = state->base.crtc->dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	dev_priv->display.load_luts(crtc_state);
+	dev_priv->display.load_luts(state);
 }
 
-int intel_color_check(struct drm_crtc *crtc,
-		      struct drm_crtc_state *crtc_state)
+int intel_color_check(struct intel_crtc *crtc,
+		      struct intel_crtc_state *state)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	size_t gamma_length, degamma_length;
 
 	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
@@ -627,27 +612,27 @@  int intel_color_check(struct drm_crtc *crtc,
 	 * We allow both degamma & gamma luts at the right size or
 	 * NULL.
 	 */
-	if ((!crtc_state->degamma_lut ||
-	     drm_color_lut_size(crtc_state->degamma_lut) == degamma_length) &&
-	    (!crtc_state->gamma_lut ||
-	     drm_color_lut_size(crtc_state->gamma_lut) == gamma_length))
+	if ((!state->base.degamma_lut ||
+	     drm_color_lut_size(state->base.degamma_lut) == degamma_length) &&
+	    (!state->base.gamma_lut ||
+	     drm_color_lut_size(state->base.gamma_lut) == gamma_length))
 		return 0;
 
 	/*
 	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
 	 * size (256 entries).
 	 */
-	if (crtc_state_is_legacy_gamma(crtc_state))
+	if (crtc_state_is_legacy_gamma(state))
 		return 0;
 
 	return -EINVAL;
 }
 
-void intel_color_init(struct drm_crtc *crtc)
+void intel_color_init(struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	drm_mode_crtc_set_gamma_size(crtc, 256);
+	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
 
 	if (IS_CHERRYVIEW(dev_priv)) {
 		dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
@@ -669,7 +654,7 @@  void intel_color_init(struct drm_crtc *crtc)
 	/* Enable color management support when we have degamma & gamma LUTs. */
 	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
 	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
-		drm_crtc_enable_color_mgmt(crtc,
+		drm_crtc_enable_color_mgmt(&crtc->base,
 					   INTEL_INFO(dev_priv)->color.degamma_lut_size,
 					   true,
 					   INTEL_INFO(dev_priv)->color.gamma_lut_size);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index db6004a883c7..5b965797df4e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5641,7 +5641,7 @@  static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
 	 * On ILK+ LUT must be loaded before the pipe is running but with
 	 * clocks enabled
 	 */
-	intel_color_load_luts(&pipe_config->base);
+	intel_color_load_luts(pipe_config);
 
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
@@ -5752,7 +5752,7 @@  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	haswell_set_pipemisc(pipe_config);
 
-	intel_color_set_csc(&pipe_config->base);
+	intel_color_set_csc(pipe_config);
 
 	intel_crtc->active = true;
 
@@ -5771,7 +5771,7 @@  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	 * On ILK+ LUT must be loaded before the pipe is running but with
 	 * clocks enabled
 	 */
-	intel_color_load_luts(&pipe_config->base);
+	intel_color_load_luts(pipe_config);
 
 	/*
 	 * Display WA #1153: enable hardware to bypass the alpha math
@@ -6117,7 +6117,7 @@  static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	i9xx_set_pipeconf(pipe_config);
 
-	intel_color_set_csc(&pipe_config->base);
+	intel_color_set_csc(pipe_config);
 
 	intel_crtc->active = true;
 
@@ -6137,7 +6137,7 @@  static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	i9xx_pfit_enable(pipe_config);
 
-	intel_color_load_luts(&pipe_config->base);
+	intel_color_load_luts(pipe_config);
 
 	dev_priv->display.initial_watermarks(old_intel_state,
 					     pipe_config);
@@ -6193,7 +6193,7 @@  static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	i9xx_pfit_enable(pipe_config);
 
-	intel_color_load_luts(&pipe_config->base);
+	intel_color_load_luts(pipe_config);
 
 	if (dev_priv->display.initial_watermarks != NULL)
 		dev_priv->display.initial_watermarks(old_intel_state,
@@ -10972,7 +10972,7 @@  static int intel_crtc_atomic_check(struct drm_crtc *crtc,
 	}
 
 	if (crtc_state->color_mgmt_changed) {
-		ret = intel_color_check(crtc, crtc_state);
+		ret = intel_color_check(intel_crtc, pipe_config);
 		if (ret)
 			return ret;
 
@@ -13548,8 +13548,8 @@  static void intel_begin_crtc_commit(struct drm_crtc *crtc,
 	if (!modeset &&
 	    (intel_cstate->base.color_mgmt_changed ||
 	     intel_cstate->update_pipe)) {
-		intel_color_set_csc(&intel_cstate->base);
-		intel_color_load_luts(&intel_cstate->base);
+		intel_color_set_csc(intel_cstate);
+		intel_color_load_luts(intel_cstate);
 	}
 
 	/* Perform vblank evasion around commit operation */
@@ -14122,7 +14122,7 @@  static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
 
-	intel_color_init(&intel_crtc->base);
+	intel_color_init(intel_crtc);
 
 	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a8177ccf1d4f..ba1d97991d5a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2327,10 +2327,10 @@  int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 					struct intel_plane_state *intel_state);
 
 /* intel_color.c */
-void intel_color_init(struct drm_crtc *crtc);
-int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
-void intel_color_set_csc(struct drm_crtc_state *crtc_state);
-void intel_color_load_luts(struct drm_crtc_state *crtc_state);
+void intel_color_init(struct intel_crtc *crtc);
+int intel_color_check(struct intel_crtc *crtc, struct intel_crtc_state *state);
+void intel_color_set_csc(struct intel_crtc_state *state);
+void intel_color_load_luts(struct intel_crtc_state *state);
 
 /* intel_lspcon.c */
 bool lspcon_init(struct intel_digital_port *intel_dig_port);

Comments

Ville Syrjälä Dec. 10, 2018, 7:31 p.m.
On Thu, Dec 06, 2018 at 04:54:01PM -0800, Matt Roper wrote:
> Try to be more consistent about intel_* types rather than drm_* types
> for lower-level driver functions.  While we're at it, let's also be more
> consistent with state variable naming (half of the platforms use the
> name 'state' whereas the other half used 'crtc_state').
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |   4 +-
>  drivers/gpu/drm/i915/intel_color.c   | 207 ++++++++++++++++-------------------
>  drivers/gpu/drm/i915/intel_display.c |  20 ++--
>  drivers/gpu/drm/i915/intel_drv.h     |   8 +-
>  4 files changed, 112 insertions(+), 127 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7469a7785253..48fb5e9bd08b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -321,8 +321,8 @@ struct drm_i915_display_funcs {
>  	/* display clock increase/decrease */
>  	/* pll clock increase/decrease */
>  
> -	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
> -	void (*load_luts)(struct drm_crtc_state *crtc_state);
> +	void (*load_csc_matrix)(struct intel_crtc_state *state);
> +	void (*load_luts)(struct intel_crtc_state *state);
>  };
>  
>  #define CSR_VERSION(major, minor)	((major) << 16 | (minor))
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5127da286a2b..335c4702fcfb 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -74,12 +74,12 @@
>  #define ILK_CSC_COEFF_1_0		\
>  	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>  
> -static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state)
> +static bool crtc_state_is_legacy_gamma(struct intel_crtc_state *state)

I'd lkike s/state/crtc_state/, at least in the cases where it doesn't
make the diff too noisy.

Or maybe even follow up with a wholesale sed/cocci job to just rename
everything in the file?

Patch is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  {
> -	return !state->degamma_lut &&
> -		!state->ctm &&
> -		state->gamma_lut &&
> -		drm_color_lut_size(state->gamma_lut) == LEGACY_LUT_LENGTH;
> +	return !state->base.degamma_lut &&
> +		!state->base.ctm &&
> +		state->base.gamma_lut &&
> +		drm_color_lut_size(state->base.gamma_lut) == LEGACY_LUT_LENGTH;
>  }
>  
>  /*
> @@ -108,10 +108,10 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
>  	return result;
>  }
>  
> -static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
> +static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>  {
> -	int pipe = intel_crtc->pipe;
> -	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> +	int pipe = crtc->pipe;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>  	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>  	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
> @@ -132,14 +132,12 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
>  	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>  }
>  
> -static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
> +static void ilk_load_csc_matrix(struct intel_crtc_state *state)
>  {
> -	struct drm_crtc *crtc = crtc_state->crtc;
> -	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	int i, pipe = intel_crtc->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	int i, pipe = crtc->pipe;
>  	uint16_t coeffs[9] = { 0, };
> -	struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
>  	bool limited_color_range = false;
>  
>  	/*
> @@ -147,14 +145,14 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
>  	 * do the range compression using the gamma LUT instead.
>  	 */
>  	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> -		limited_color_range = intel_crtc_state->limited_color_range;
> +		limited_color_range = state->limited_color_range;
>  
> -	if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> -	    intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> -		ilk_load_ycbcr_conversion_matrix(intel_crtc);
> +	if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> +	    state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> +		ilk_load_ycbcr_conversion_matrix(crtc);
>  		return;
> -	} else if (crtc_state->ctm) {
> -		struct drm_color_ctm *ctm = crtc_state->ctm->data;
> +	} else if (state->base.ctm) {
> +		struct drm_color_ctm *ctm = state->base.ctm->data;
>  		const u64 *input;
>  		u64 temp[9];
>  
> @@ -253,16 +251,15 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
>  /*
>   * Set up the pipe CSC unit on CherryView.
>   */
> -static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
> +static void cherryview_load_csc_matrix(struct intel_crtc_state *state)
>  {
> -	struct drm_crtc *crtc = state->crtc;
> -	struct drm_device *dev = crtc->dev;
> +	struct drm_device *dev = state->base.crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	int pipe = to_intel_crtc(crtc)->pipe;
> +	int pipe = to_intel_crtc(state->base.crtc)->pipe;
>  	uint32_t mode;
>  
> -	if (state->ctm) {
> -		struct drm_color_ctm *ctm = state->ctm->data;
> +	if (state->base.ctm) {
> +		struct drm_color_ctm *ctm = state->base.ctm->data;
>  		uint16_t coeffs[9] = { 0, };
>  		int i;
>  
> @@ -293,36 +290,34 @@ static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
>  		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
>  	}
>  
> -	mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
> +	mode = (state->base.ctm ? CGM_PIPE_MODE_CSC : 0);
>  	if (!crtc_state_is_legacy_gamma(state)) {
> -		mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> -			(state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
> +		mode |= (state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> +			(state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
>  	}
>  	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
>  }
>  
> -void intel_color_set_csc(struct drm_crtc_state *crtc_state)
> +void intel_color_set_csc(struct intel_crtc_state *state)
>  {
> -	struct drm_device *dev = crtc_state->crtc->dev;
> +	struct drm_device *dev = state->base.crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
>  	if (dev_priv->display.load_csc_matrix)
> -		dev_priv->display.load_csc_matrix(crtc_state);
> +		dev_priv->display.load_csc_matrix(state);
>  }
>  
>  /* Loads the legacy palette/gamma unit for the CRTC. */
> -static void i9xx_load_luts_internal(struct drm_crtc *crtc,
> -				    struct drm_property_blob *blob,
> -				    struct intel_crtc_state *crtc_state)
> +static void i9xx_load_luts_internal(struct intel_crtc_state *state,
> +				    struct drm_property_blob *blob)
>  {
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	enum pipe pipe = intel_crtc->pipe;
> +	struct intel_crtc *crtc = to_intel_crtc(state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
>  	int i;
>  
>  	if (HAS_GMCH_DISPLAY(dev_priv)) {
> -		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> +		if (intel_crtc_has_type(state, INTEL_OUTPUT_DSI))
>  			assert_dsi_pll_enabled(dev_priv);
>  		else
>  			assert_pll_enabled(dev_priv, pipe);
> @@ -353,53 +348,48 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
>  	}
>  }
>  
> -static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
> +static void i9xx_load_luts(struct intel_crtc_state *state)
>  {
> -	i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
> -				to_intel_crtc_state(crtc_state));
> +	i9xx_load_luts_internal(state, state->base.gamma_lut);
>  }
>  
>  /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
> -static void haswell_load_luts(struct drm_crtc_state *crtc_state)
> +static void haswell_load_luts(struct intel_crtc_state *state)
>  {
> -	struct drm_crtc *crtc = crtc_state->crtc;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct intel_crtc_state *intel_crtc_state =
> -		to_intel_crtc_state(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(state->base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	bool reenable_ips = false;
>  
>  	/*
>  	 * Workaround : Do not read or write the pipe palette/gamma data while
>  	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
>  	 */
> -	if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
> -	    (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
> -		hsw_disable_ips(intel_crtc_state);
> +	if (IS_HASWELL(dev_priv) && state->ips_enabled &&
> +	    (state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
> +		hsw_disable_ips(state);
>  		reenable_ips = true;
>  	}
>  
> -	intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> -	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
> +	state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> +	I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
>  
> -	i9xx_load_luts(crtc_state);
> +	i9xx_load_luts(state);
>  
>  	if (reenable_ips)
> -		hsw_enable_ips(intel_crtc_state);
> +		hsw_enable_ips(state);
>  }
>  
> -static void bdw_load_degamma_lut(struct drm_crtc_state *state)
> +static void bdw_load_degamma_lut(struct intel_crtc_state *state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> -	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> +	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
> +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
>  	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  
>  	I915_WRITE(PREC_PAL_INDEX(pipe),
>  		   PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
>  
> -	if (state->degamma_lut) {
> -		struct drm_color_lut *lut = state->degamma_lut->data;
> +	if (state->base.degamma_lut) {
> +		struct drm_color_lut *lut = state->base.degamma_lut->data;
>  
>  		for (i = 0; i < lut_size; i++) {
>  			uint32_t word =
> @@ -419,10 +409,10 @@ static void bdw_load_degamma_lut(struct drm_crtc_state *state)
>  	}
>  }
>  
> -static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
> +static void bdw_load_gamma_lut(struct intel_crtc_state *state, u32 offset)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> -	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> +	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
> +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
>  	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  
>  	WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
> @@ -432,8 +422,8 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
>  		   PAL_PREC_AUTO_INCREMENT |
>  		   offset);
>  
> -	if (state->gamma_lut) {
> -		struct drm_color_lut *lut = state->gamma_lut->data;
> +	if (state->base.gamma_lut) {
> +		struct drm_color_lut *lut = state->base.gamma_lut->data;
>  
>  		for (i = 0; i < lut_size; i++) {
>  			uint32_t word =
> @@ -467,11 +457,10 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
>  }
>  
>  /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
> -static void broadwell_load_luts(struct drm_crtc_state *state)
> +static void broadwell_load_luts(struct intel_crtc_state *state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> -	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
> -	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> +	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
> +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
>  
>  	if (crtc_state_is_legacy_gamma(state)) {
>  		haswell_load_luts(state);
> @@ -479,10 +468,9 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
>  	}
>  
>  	bdw_load_degamma_lut(state);
> -	bdw_load_gamma_lut(state,
> -			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
> +	bdw_load_gamma_lut(state, INTEL_INFO(dev_priv)->color.degamma_lut_size);
>  
> -	intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> +	state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
>  	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
>  	POSTING_READ(GAMMA_MODE(pipe));
>  
> @@ -493,10 +481,10 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
>  	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
>  }
>  
> -static void glk_load_degamma_lut(struct drm_crtc_state *state)
> +static void glk_load_degamma_lut(struct intel_crtc_state *state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> -	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> +	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
> +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
>  	const uint32_t lut_size = 33;
>  	uint32_t i;
>  
> @@ -523,13 +511,11 @@ static void glk_load_degamma_lut(struct drm_crtc_state *state)
>  		I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
>  }
>  
> -static void glk_load_luts(struct drm_crtc_state *state)
> +static void glk_load_luts(struct intel_crtc_state *state)
>  {
> -	struct drm_crtc *crtc = state->crtc;
> -	struct drm_device *dev = crtc->dev;
> +	struct drm_device *dev = state->base.crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
>  
>  	glk_load_degamma_lut(state);
>  
> @@ -540,15 +526,15 @@ static void glk_load_luts(struct drm_crtc_state *state)
>  
>  	bdw_load_gamma_lut(state, 0);
>  
> -	intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> +	state->gamma_mode = GAMMA_MODE_MODE_10BIT;
>  	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
>  	POSTING_READ(GAMMA_MODE(pipe));
>  }
>  
>  /* Loads the palette/gamma unit for the CRTC on CherryView. */
> -static void cherryview_load_luts(struct drm_crtc_state *state)
> +static void cherryview_load_luts(struct intel_crtc_state *state)
>  {
> -	struct drm_crtc *crtc = state->crtc;
> +	struct drm_crtc *crtc = state->base.crtc;
>  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>  	struct drm_color_lut *lut;
> @@ -558,14 +544,13 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>  	if (crtc_state_is_legacy_gamma(state)) {
>  		/* Turn off degamma/gamma on CGM block. */
>  		I915_WRITE(CGM_PIPE_MODE(pipe),
> -			   (state->ctm ? CGM_PIPE_MODE_CSC : 0));
> -		i9xx_load_luts_internal(crtc, state->gamma_lut,
> -					to_intel_crtc_state(state));
> +			   (state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
> +		i9xx_load_luts_internal(state, state->base.gamma_lut);
>  		return;
>  	}
>  
> -	if (state->degamma_lut) {
> -		lut = state->degamma_lut->data;
> +	if (state->base.degamma_lut) {
> +		lut = state->base.degamma_lut->data;
>  		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  		for (i = 0; i < lut_size; i++) {
>  			/* Write LUT in U0.14 format. */
> @@ -579,8 +564,8 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>  		}
>  	}
>  
> -	if (state->gamma_lut) {
> -		lut = state->gamma_lut->data;
> +	if (state->base.gamma_lut) {
> +		lut = state->base.gamma_lut->data;
>  		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  		for (i = 0; i < lut_size; i++) {
>  			/* Write LUT in U0.10 format. */
> @@ -595,29 +580,29 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>  	}
>  
>  	I915_WRITE(CGM_PIPE_MODE(pipe),
> -		   (state->ctm ? CGM_PIPE_MODE_CSC : 0) |
> -		   (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> -		   (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
> +		   (state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
> +		   (state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> +		   (state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
>  
>  	/*
>  	 * Also program a linear LUT in the legacy block (behind the
>  	 * CGM block).
>  	 */
> -	i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
> +	i9xx_load_luts_internal(state, NULL);
>  }
>  
> -void intel_color_load_luts(struct drm_crtc_state *crtc_state)
> +void intel_color_load_luts(struct intel_crtc_state *state)
>  {
> -	struct drm_device *dev = crtc_state->crtc->dev;
> +	struct drm_device *dev = state->base.crtc->dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	dev_priv->display.load_luts(crtc_state);
> +	dev_priv->display.load_luts(state);
>  }
>  
> -int intel_color_check(struct drm_crtc *crtc,
> -		      struct drm_crtc_state *crtc_state)
> +int intel_color_check(struct intel_crtc *crtc,
> +		      struct intel_crtc_state *state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	size_t gamma_length, degamma_length;
>  
>  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> @@ -627,27 +612,27 @@ int intel_color_check(struct drm_crtc *crtc,
>  	 * We allow both degamma & gamma luts at the right size or
>  	 * NULL.
>  	 */
> -	if ((!crtc_state->degamma_lut ||
> -	     drm_color_lut_size(crtc_state->degamma_lut) == degamma_length) &&
> -	    (!crtc_state->gamma_lut ||
> -	     drm_color_lut_size(crtc_state->gamma_lut) == gamma_length))
> +	if ((!state->base.degamma_lut ||
> +	     drm_color_lut_size(state->base.degamma_lut) == degamma_length) &&
> +	    (!state->base.gamma_lut ||
> +	     drm_color_lut_size(state->base.gamma_lut) == gamma_length))
>  		return 0;
>  
>  	/*
>  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
>  	 * size (256 entries).
>  	 */
> -	if (crtc_state_is_legacy_gamma(crtc_state))
> +	if (crtc_state_is_legacy_gamma(state))
>  		return 0;
>  
>  	return -EINVAL;
>  }
>  
> -void intel_color_init(struct drm_crtc *crtc)
> +void intel_color_init(struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	drm_mode_crtc_set_gamma_size(crtc, 256);
> +	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
>  
>  	if (IS_CHERRYVIEW(dev_priv)) {
>  		dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
> @@ -669,7 +654,7 @@ void intel_color_init(struct drm_crtc *crtc)
>  	/* Enable color management support when we have degamma & gamma LUTs. */
>  	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
>  	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
> -		drm_crtc_enable_color_mgmt(crtc,
> +		drm_crtc_enable_color_mgmt(&crtc->base,
>  					   INTEL_INFO(dev_priv)->color.degamma_lut_size,
>  					   true,
>  					   INTEL_INFO(dev_priv)->color.gamma_lut_size);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index db6004a883c7..5b965797df4e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5641,7 +5641,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>  	 * On ILK+ LUT must be loaded before the pipe is running but with
>  	 * clocks enabled
>  	 */
> -	intel_color_load_luts(&pipe_config->base);
> +	intel_color_load_luts(pipe_config);
>  
>  	if (dev_priv->display.initial_watermarks != NULL)
>  		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
> @@ -5752,7 +5752,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	haswell_set_pipemisc(pipe_config);
>  
> -	intel_color_set_csc(&pipe_config->base);
> +	intel_color_set_csc(pipe_config);
>  
>  	intel_crtc->active = true;
>  
> @@ -5771,7 +5771,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  	 * On ILK+ LUT must be loaded before the pipe is running but with
>  	 * clocks enabled
>  	 */
> -	intel_color_load_luts(&pipe_config->base);
> +	intel_color_load_luts(pipe_config);
>  
>  	/*
>  	 * Display WA #1153: enable hardware to bypass the alpha math
> @@ -6117,7 +6117,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	i9xx_set_pipeconf(pipe_config);
>  
> -	intel_color_set_csc(&pipe_config->base);
> +	intel_color_set_csc(pipe_config);
>  
>  	intel_crtc->active = true;
>  
> @@ -6137,7 +6137,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	i9xx_pfit_enable(pipe_config);
>  
> -	intel_color_load_luts(&pipe_config->base);
> +	intel_color_load_luts(pipe_config);
>  
>  	dev_priv->display.initial_watermarks(old_intel_state,
>  					     pipe_config);
> @@ -6193,7 +6193,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	i9xx_pfit_enable(pipe_config);
>  
> -	intel_color_load_luts(&pipe_config->base);
> +	intel_color_load_luts(pipe_config);
>  
>  	if (dev_priv->display.initial_watermarks != NULL)
>  		dev_priv->display.initial_watermarks(old_intel_state,
> @@ -10972,7 +10972,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
>  	}
>  
>  	if (crtc_state->color_mgmt_changed) {
> -		ret = intel_color_check(crtc, crtc_state);
> +		ret = intel_color_check(intel_crtc, pipe_config);
>  		if (ret)
>  			return ret;
>  
> @@ -13548,8 +13548,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
>  	if (!modeset &&
>  	    (intel_cstate->base.color_mgmt_changed ||
>  	     intel_cstate->update_pipe)) {
> -		intel_color_set_csc(&intel_cstate->base);
> -		intel_color_load_luts(&intel_cstate->base);
> +		intel_color_set_csc(intel_cstate);
> +		intel_color_load_luts(intel_cstate);
>  	}
>  
>  	/* Perform vblank evasion around commit operation */
> @@ -14122,7 +14122,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
>  
> -	intel_color_init(&intel_crtc->base);
> +	intel_color_init(intel_crtc);
>  
>  	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a8177ccf1d4f..ba1d97991d5a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2327,10 +2327,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  					struct intel_plane_state *intel_state);
>  
>  /* intel_color.c */
> -void intel_color_init(struct drm_crtc *crtc);
> -int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
> -void intel_color_set_csc(struct drm_crtc_state *crtc_state);
> -void intel_color_load_luts(struct drm_crtc_state *crtc_state);
> +void intel_color_init(struct intel_crtc *crtc);
> +int intel_color_check(struct intel_crtc *crtc, struct intel_crtc_state *state);
> +void intel_color_set_csc(struct intel_crtc_state *state);
> +void intel_color_load_luts(struct intel_crtc_state *state);
>  
>  /* intel_lspcon.c */
>  bool lspcon_init(struct intel_digital_port *intel_dig_port);
> -- 
> 2.14.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Matt Roper Dec. 10, 2018, 11:07 p.m.
On Mon, Dec 10, 2018 at 09:31:55PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 06, 2018 at 04:54:01PM -0800, Matt Roper wrote:
> > Try to be more consistent about intel_* types rather than drm_* types
> > for lower-level driver functions.  While we're at it, let's also be more
> > consistent with state variable naming (half of the platforms use the
> > name 'state' whereas the other half used 'crtc_state').
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |   4 +-
> >  drivers/gpu/drm/i915/intel_color.c   | 207 ++++++++++++++++-------------------
> >  drivers/gpu/drm/i915/intel_display.c |  20 ++--
> >  drivers/gpu/drm/i915/intel_drv.h     |   8 +-
> >  4 files changed, 112 insertions(+), 127 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 7469a7785253..48fb5e9bd08b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -321,8 +321,8 @@ struct drm_i915_display_funcs {
> >  	/* display clock increase/decrease */
> >  	/* pll clock increase/decrease */
> >  
> > -	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
> > -	void (*load_luts)(struct drm_crtc_state *crtc_state);
> > +	void (*load_csc_matrix)(struct intel_crtc_state *state);
> > +	void (*load_luts)(struct intel_crtc_state *state);
> >  };
> >  
> >  #define CSR_VERSION(major, minor)	((major) << 16 | (minor))
> > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> > index 5127da286a2b..335c4702fcfb 100644
> > --- a/drivers/gpu/drm/i915/intel_color.c
> > +++ b/drivers/gpu/drm/i915/intel_color.c
> > @@ -74,12 +74,12 @@
> >  #define ILK_CSC_COEFF_1_0		\
> >  	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
> >  
> > -static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state)
> > +static bool crtc_state_is_legacy_gamma(struct intel_crtc_state *state)
> 
> I'd lkike s/state/crtc_state/, at least in the cases where it doesn't
> make the diff too noisy.
> 
> Or maybe even follow up with a wholesale sed/cocci job to just rename
> everything in the file?
> 
> Patch is
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Applied the minor tweaks you suggested and BAT still looks clean.
Pushed to dinq; thanks for the review.


Matt

> 
> >  {
> > -	return !state->degamma_lut &&
> > -		!state->ctm &&
> > -		state->gamma_lut &&
> > -		drm_color_lut_size(state->gamma_lut) == LEGACY_LUT_LENGTH;
> > +	return !state->base.degamma_lut &&
> > +		!state->base.ctm &&
> > +		state->base.gamma_lut &&
> > +		drm_color_lut_size(state->base.gamma_lut) == LEGACY_LUT_LENGTH;
> >  }
> >  
> >  /*
> > @@ -108,10 +108,10 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
> >  	return result;
> >  }
> >  
> > -static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
> > +static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
> >  {
> > -	int pipe = intel_crtc->pipe;
> > -	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> > +	int pipe = crtc->pipe;
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  
> >  	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
> >  	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
> > @@ -132,14 +132,12 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *intel_crtc)
> >  	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> >  }
> >  
> > -static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
> > +static void ilk_load_csc_matrix(struct intel_crtc_state *state)
> >  {
> > -	struct drm_crtc *crtc = crtc_state->crtc;
> > -	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	int i, pipe = intel_crtc->pipe;
> > +	struct intel_crtc *crtc = to_intel_crtc(state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	int i, pipe = crtc->pipe;
> >  	uint16_t coeffs[9] = { 0, };
> > -	struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
> >  	bool limited_color_range = false;
> >  
> >  	/*
> > @@ -147,14 +145,14 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
> >  	 * do the range compression using the gamma LUT instead.
> >  	 */
> >  	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> > -		limited_color_range = intel_crtc_state->limited_color_range;
> > +		limited_color_range = state->limited_color_range;
> >  
> > -	if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> > -	    intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> > -		ilk_load_ycbcr_conversion_matrix(intel_crtc);
> > +	if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> > +	    state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> > +		ilk_load_ycbcr_conversion_matrix(crtc);
> >  		return;
> > -	} else if (crtc_state->ctm) {
> > -		struct drm_color_ctm *ctm = crtc_state->ctm->data;
> > +	} else if (state->base.ctm) {
> > +		struct drm_color_ctm *ctm = state->base.ctm->data;
> >  		const u64 *input;
> >  		u64 temp[9];
> >  
> > @@ -253,16 +251,15 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
> >  /*
> >   * Set up the pipe CSC unit on CherryView.
> >   */
> > -static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
> > +static void cherryview_load_csc_matrix(struct intel_crtc_state *state)
> >  {
> > -	struct drm_crtc *crtc = state->crtc;
> > -	struct drm_device *dev = crtc->dev;
> > +	struct drm_device *dev = state->base.crtc->dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	int pipe = to_intel_crtc(crtc)->pipe;
> > +	int pipe = to_intel_crtc(state->base.crtc)->pipe;
> >  	uint32_t mode;
> >  
> > -	if (state->ctm) {
> > -		struct drm_color_ctm *ctm = state->ctm->data;
> > +	if (state->base.ctm) {
> > +		struct drm_color_ctm *ctm = state->base.ctm->data;
> >  		uint16_t coeffs[9] = { 0, };
> >  		int i;
> >  
> > @@ -293,36 +290,34 @@ static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
> >  		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
> >  	}
> >  
> > -	mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
> > +	mode = (state->base.ctm ? CGM_PIPE_MODE_CSC : 0);
> >  	if (!crtc_state_is_legacy_gamma(state)) {
> > -		mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> > -			(state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
> > +		mode |= (state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> > +			(state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
> >  	}
> >  	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
> >  }
> >  
> > -void intel_color_set_csc(struct drm_crtc_state *crtc_state)
> > +void intel_color_set_csc(struct intel_crtc_state *state)
> >  {
> > -	struct drm_device *dev = crtc_state->crtc->dev;
> > +	struct drm_device *dev = state->base.crtc->dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  
> >  	if (dev_priv->display.load_csc_matrix)
> > -		dev_priv->display.load_csc_matrix(crtc_state);
> > +		dev_priv->display.load_csc_matrix(state);
> >  }
> >  
> >  /* Loads the legacy palette/gamma unit for the CRTC. */
> > -static void i9xx_load_luts_internal(struct drm_crtc *crtc,
> > -				    struct drm_property_blob *blob,
> > -				    struct intel_crtc_state *crtc_state)
> > +static void i9xx_load_luts_internal(struct intel_crtc_state *state,
> > +				    struct drm_property_blob *blob)
> >  {
> > -	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	enum pipe pipe = intel_crtc->pipe;
> > +	struct intel_crtc *crtc = to_intel_crtc(state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	enum pipe pipe = crtc->pipe;
> >  	int i;
> >  
> >  	if (HAS_GMCH_DISPLAY(dev_priv)) {
> > -		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > +		if (intel_crtc_has_type(state, INTEL_OUTPUT_DSI))
> >  			assert_dsi_pll_enabled(dev_priv);
> >  		else
> >  			assert_pll_enabled(dev_priv, pipe);
> > @@ -353,53 +348,48 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
> >  	}
> >  }
> >  
> > -static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
> > +static void i9xx_load_luts(struct intel_crtc_state *state)
> >  {
> > -	i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
> > -				to_intel_crtc_state(crtc_state));
> > +	i9xx_load_luts_internal(state, state->base.gamma_lut);
> >  }
> >  
> >  /* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
> > -static void haswell_load_luts(struct drm_crtc_state *crtc_state)
> > +static void haswell_load_luts(struct intel_crtc_state *state)
> >  {
> > -	struct drm_crtc *crtc = crtc_state->crtc;
> > -	struct drm_device *dev = crtc->dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > -	struct intel_crtc_state *intel_crtc_state =
> > -		to_intel_crtc_state(crtc_state);
> > +	struct intel_crtc *crtc = to_intel_crtc(state->base.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	bool reenable_ips = false;
> >  
> >  	/*
> >  	 * Workaround : Do not read or write the pipe palette/gamma data while
> >  	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> >  	 */
> > -	if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
> > -	    (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
> > -		hsw_disable_ips(intel_crtc_state);
> > +	if (IS_HASWELL(dev_priv) && state->ips_enabled &&
> > +	    (state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
> > +		hsw_disable_ips(state);
> >  		reenable_ips = true;
> >  	}
> >  
> > -	intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> > -	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
> > +	state->gamma_mode = GAMMA_MODE_MODE_8BIT;
> > +	I915_WRITE(GAMMA_MODE(crtc->pipe), GAMMA_MODE_MODE_8BIT);
> >  
> > -	i9xx_load_luts(crtc_state);
> > +	i9xx_load_luts(state);
> >  
> >  	if (reenable_ips)
> > -		hsw_enable_ips(intel_crtc_state);
> > +		hsw_enable_ips(state);
> >  }
> >  
> > -static void bdw_load_degamma_lut(struct drm_crtc_state *state)
> > +static void bdw_load_degamma_lut(struct intel_crtc_state *state)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> > -	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
> > +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
> >  	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> >  
> >  	I915_WRITE(PREC_PAL_INDEX(pipe),
> >  		   PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
> >  
> > -	if (state->degamma_lut) {
> > -		struct drm_color_lut *lut = state->degamma_lut->data;
> > +	if (state->base.degamma_lut) {
> > +		struct drm_color_lut *lut = state->base.degamma_lut->data;
> >  
> >  		for (i = 0; i < lut_size; i++) {
> >  			uint32_t word =
> > @@ -419,10 +409,10 @@ static void bdw_load_degamma_lut(struct drm_crtc_state *state)
> >  	}
> >  }
> >  
> > -static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
> > +static void bdw_load_gamma_lut(struct intel_crtc_state *state, u32 offset)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> > -	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
> > +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
> >  	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> >  
> >  	WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
> > @@ -432,8 +422,8 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
> >  		   PAL_PREC_AUTO_INCREMENT |
> >  		   offset);
> >  
> > -	if (state->gamma_lut) {
> > -		struct drm_color_lut *lut = state->gamma_lut->data;
> > +	if (state->base.gamma_lut) {
> > +		struct drm_color_lut *lut = state->base.gamma_lut->data;
> >  
> >  		for (i = 0; i < lut_size; i++) {
> >  			uint32_t word =
> > @@ -467,11 +457,10 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
> >  }
> >  
> >  /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
> > -static void broadwell_load_luts(struct drm_crtc_state *state)
> > +static void broadwell_load_luts(struct intel_crtc_state *state)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> > -	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
> > -	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
> > +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
> >  
> >  	if (crtc_state_is_legacy_gamma(state)) {
> >  		haswell_load_luts(state);
> > @@ -479,10 +468,9 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
> >  	}
> >  
> >  	bdw_load_degamma_lut(state);
> > -	bdw_load_gamma_lut(state,
> > -			   INTEL_INFO(dev_priv)->color.degamma_lut_size);
> > +	bdw_load_gamma_lut(state, INTEL_INFO(dev_priv)->color.degamma_lut_size);
> >  
> > -	intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> > +	state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> >  	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
> >  	POSTING_READ(GAMMA_MODE(pipe));
> >  
> > @@ -493,10 +481,10 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
> >  	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
> >  }
> >  
> > -static void glk_load_degamma_lut(struct drm_crtc_state *state)
> > +static void glk_load_degamma_lut(struct intel_crtc_state *state)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> > -	enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.crtc->dev);
> > +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
> >  	const uint32_t lut_size = 33;
> >  	uint32_t i;
> >  
> > @@ -523,13 +511,11 @@ static void glk_load_degamma_lut(struct drm_crtc_state *state)
> >  		I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
> >  }
> >  
> > -static void glk_load_luts(struct drm_crtc_state *state)
> > +static void glk_load_luts(struct intel_crtc_state *state)
> >  {
> > -	struct drm_crtc *crtc = state->crtc;
> > -	struct drm_device *dev = crtc->dev;
> > +	struct drm_device *dev = state->base.crtc->dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > -	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
> > -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > +	enum pipe pipe = to_intel_crtc(state->base.crtc)->pipe;
> >  
> >  	glk_load_degamma_lut(state);
> >  
> > @@ -540,15 +526,15 @@ static void glk_load_luts(struct drm_crtc_state *state)
> >  
> >  	bdw_load_gamma_lut(state, 0);
> >  
> > -	intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> > +	state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> >  	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);
> >  	POSTING_READ(GAMMA_MODE(pipe));
> >  }
> >  
> >  /* Loads the palette/gamma unit for the CRTC on CherryView. */
> > -static void cherryview_load_luts(struct drm_crtc_state *state)
> > +static void cherryview_load_luts(struct intel_crtc_state *state)
> >  {
> > -	struct drm_crtc *crtc = state->crtc;
> > +	struct drm_crtc *crtc = state->base.crtc;
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> >  	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> >  	struct drm_color_lut *lut;
> > @@ -558,14 +544,13 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
> >  	if (crtc_state_is_legacy_gamma(state)) {
> >  		/* Turn off degamma/gamma on CGM block. */
> >  		I915_WRITE(CGM_PIPE_MODE(pipe),
> > -			   (state->ctm ? CGM_PIPE_MODE_CSC : 0));
> > -		i9xx_load_luts_internal(crtc, state->gamma_lut,
> > -					to_intel_crtc_state(state));
> > +			   (state->base.ctm ? CGM_PIPE_MODE_CSC : 0));
> > +		i9xx_load_luts_internal(state, state->base.gamma_lut);
> >  		return;
> >  	}
> >  
> > -	if (state->degamma_lut) {
> > -		lut = state->degamma_lut->data;
> > +	if (state->base.degamma_lut) {
> > +		lut = state->base.degamma_lut->data;
> >  		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> >  		for (i = 0; i < lut_size; i++) {
> >  			/* Write LUT in U0.14 format. */
> > @@ -579,8 +564,8 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
> >  		}
> >  	}
> >  
> > -	if (state->gamma_lut) {
> > -		lut = state->gamma_lut->data;
> > +	if (state->base.gamma_lut) {
> > +		lut = state->base.gamma_lut->data;
> >  		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> >  		for (i = 0; i < lut_size; i++) {
> >  			/* Write LUT in U0.10 format. */
> > @@ -595,29 +580,29 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
> >  	}
> >  
> >  	I915_WRITE(CGM_PIPE_MODE(pipe),
> > -		   (state->ctm ? CGM_PIPE_MODE_CSC : 0) |
> > -		   (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> > -		   (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
> > +		   (state->base.ctm ? CGM_PIPE_MODE_CSC : 0) |
> > +		   (state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
> > +		   (state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
> >  
> >  	/*
> >  	 * Also program a linear LUT in the legacy block (behind the
> >  	 * CGM block).
> >  	 */
> > -	i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
> > +	i9xx_load_luts_internal(state, NULL);
> >  }
> >  
> > -void intel_color_load_luts(struct drm_crtc_state *crtc_state)
> > +void intel_color_load_luts(struct intel_crtc_state *state)
> >  {
> > -	struct drm_device *dev = crtc_state->crtc->dev;
> > +	struct drm_device *dev = state->base.crtc->dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> >  
> > -	dev_priv->display.load_luts(crtc_state);
> > +	dev_priv->display.load_luts(state);
> >  }
> >  
> > -int intel_color_check(struct drm_crtc *crtc,
> > -		      struct drm_crtc_state *crtc_state)
> > +int intel_color_check(struct intel_crtc *crtc,
> > +		      struct intel_crtc_state *state)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	size_t gamma_length, degamma_length;
> >  
> >  	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> > @@ -627,27 +612,27 @@ int intel_color_check(struct drm_crtc *crtc,
> >  	 * We allow both degamma & gamma luts at the right size or
> >  	 * NULL.
> >  	 */
> > -	if ((!crtc_state->degamma_lut ||
> > -	     drm_color_lut_size(crtc_state->degamma_lut) == degamma_length) &&
> > -	    (!crtc_state->gamma_lut ||
> > -	     drm_color_lut_size(crtc_state->gamma_lut) == gamma_length))
> > +	if ((!state->base.degamma_lut ||
> > +	     drm_color_lut_size(state->base.degamma_lut) == degamma_length) &&
> > +	    (!state->base.gamma_lut ||
> > +	     drm_color_lut_size(state->base.gamma_lut) == gamma_length))
> >  		return 0;
> >  
> >  	/*
> >  	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
> >  	 * size (256 entries).
> >  	 */
> > -	if (crtc_state_is_legacy_gamma(crtc_state))
> > +	if (crtc_state_is_legacy_gamma(state))
> >  		return 0;
> >  
> >  	return -EINVAL;
> >  }
> >  
> > -void intel_color_init(struct drm_crtc *crtc)
> > +void intel_color_init(struct intel_crtc *crtc)
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  
> > -	drm_mode_crtc_set_gamma_size(crtc, 256);
> > +	drm_mode_crtc_set_gamma_size(&crtc->base, 256);
> >  
> >  	if (IS_CHERRYVIEW(dev_priv)) {
> >  		dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
> > @@ -669,7 +654,7 @@ void intel_color_init(struct drm_crtc *crtc)
> >  	/* Enable color management support when we have degamma & gamma LUTs. */
> >  	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
> >  	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
> > -		drm_crtc_enable_color_mgmt(crtc,
> > +		drm_crtc_enable_color_mgmt(&crtc->base,
> >  					   INTEL_INFO(dev_priv)->color.degamma_lut_size,
> >  					   true,
> >  					   INTEL_INFO(dev_priv)->color.gamma_lut_size);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index db6004a883c7..5b965797df4e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5641,7 +5641,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> >  	 * On ILK+ LUT must be loaded before the pipe is running but with
> >  	 * clocks enabled
> >  	 */
> > -	intel_color_load_luts(&pipe_config->base);
> > +	intel_color_load_luts(pipe_config);
> >  
> >  	if (dev_priv->display.initial_watermarks != NULL)
> >  		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
> > @@ -5752,7 +5752,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> >  
> >  	haswell_set_pipemisc(pipe_config);
> >  
> > -	intel_color_set_csc(&pipe_config->base);
> > +	intel_color_set_csc(pipe_config);
> >  
> >  	intel_crtc->active = true;
> >  
> > @@ -5771,7 +5771,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> >  	 * On ILK+ LUT must be loaded before the pipe is running but with
> >  	 * clocks enabled
> >  	 */
> > -	intel_color_load_luts(&pipe_config->base);
> > +	intel_color_load_luts(pipe_config);
> >  
> >  	/*
> >  	 * Display WA #1153: enable hardware to bypass the alpha math
> > @@ -6117,7 +6117,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> >  
> >  	i9xx_set_pipeconf(pipe_config);
> >  
> > -	intel_color_set_csc(&pipe_config->base);
> > +	intel_color_set_csc(pipe_config);
> >  
> >  	intel_crtc->active = true;
> >  
> > @@ -6137,7 +6137,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> >  
> >  	i9xx_pfit_enable(pipe_config);
> >  
> > -	intel_color_load_luts(&pipe_config->base);
> > +	intel_color_load_luts(pipe_config);
> >  
> >  	dev_priv->display.initial_watermarks(old_intel_state,
> >  					     pipe_config);
> > @@ -6193,7 +6193,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
> >  
> >  	i9xx_pfit_enable(pipe_config);
> >  
> > -	intel_color_load_luts(&pipe_config->base);
> > +	intel_color_load_luts(pipe_config);
> >  
> >  	if (dev_priv->display.initial_watermarks != NULL)
> >  		dev_priv->display.initial_watermarks(old_intel_state,
> > @@ -10972,7 +10972,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> >  	}
> >  
> >  	if (crtc_state->color_mgmt_changed) {
> > -		ret = intel_color_check(crtc, crtc_state);
> > +		ret = intel_color_check(intel_crtc, pipe_config);
> >  		if (ret)
> >  			return ret;
> >  
> > @@ -13548,8 +13548,8 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
> >  	if (!modeset &&
> >  	    (intel_cstate->base.color_mgmt_changed ||
> >  	     intel_cstate->update_pipe)) {
> > -		intel_color_set_csc(&intel_cstate->base);
> > -		intel_color_load_luts(&intel_cstate->base);
> > +		intel_color_set_csc(intel_cstate);
> > +		intel_color_load_luts(intel_cstate);
> >  	}
> >  
> >  	/* Perform vblank evasion around commit operation */
> > @@ -14122,7 +14122,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> >  
> >  	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
> >  
> > -	intel_color_init(&intel_crtc->base);
> > +	intel_color_init(intel_crtc);
> >  
> >  	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index a8177ccf1d4f..ba1d97991d5a 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -2327,10 +2327,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> >  					struct intel_plane_state *intel_state);
> >  
> >  /* intel_color.c */
> > -void intel_color_init(struct drm_crtc *crtc);
> > -int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
> > -void intel_color_set_csc(struct drm_crtc_state *crtc_state);
> > -void intel_color_load_luts(struct drm_crtc_state *crtc_state);
> > +void intel_color_init(struct intel_crtc *crtc);
> > +int intel_color_check(struct intel_crtc *crtc, struct intel_crtc_state *state);
> > +void intel_color_set_csc(struct intel_crtc_state *state);
> > +void intel_color_load_luts(struct intel_crtc_state *state);
> >  
> >  /* intel_lspcon.c */
> >  bool lspcon_init(struct intel_digital_port *intel_dig_port);
> > -- 
> > 2.14.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel