drm/i915/execlists: Move RCS mmio workaround to new common wa_list

Submitted by Chris Wilson on Dec. 6, 2018, 12:56 p.m.

Details

Message ID 20181206125607.9092-1-chris@chris-wilson.co.uk
State New
Series "drm/i915/execlists: Move RCS mmio workaround to new common wa_list"
Headers show

Commit Message

Chris Wilson Dec. 6, 2018, 12:56 p.m.
We can move the remaining RCS workarounds applied to only gen8 to the
engine->wa_list, and then reduce all engine->init_hw callbacks to common
code. The benefit of using the new wa_list is that we verify that the
registers are indeed restored and keep their magic values.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c         | 42 +-----------------------
 drivers/gpu/drm/i915/intel_workarounds.c | 14 ++++++++
 2 files changed, 15 insertions(+), 41 deletions(-)

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diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0b64bc38f66f..31f378cf5525 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1671,6 +1671,7 @@  static bool unexpected_starting_state(struct intel_engine_cs *engine)
 static int gen8_init_common_ring(struct intel_engine_cs *engine)
 {
 	intel_engine_apply_workarounds(engine);
+	intel_engine_apply_whitelist(engine);
 
 	intel_mocs_init_engine(engine);
 
@@ -1687,43 +1688,6 @@  static int gen8_init_common_ring(struct intel_engine_cs *engine)
 	return 0;
 }
 
-static int gen8_init_render_ring(struct intel_engine_cs *engine)
-{
-	struct drm_i915_private *dev_priv = engine->i915;
-	int ret;
-
-	ret = gen8_init_common_ring(engine);
-	if (ret)
-		return ret;
-
-	intel_engine_apply_whitelist(engine);
-
-	/* We need to disable the AsyncFlip performance optimisations in order
-	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
-	 * programmed to '1' on all products.
-	 *
-	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
-	 */
-	I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
-
-	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
-
-	return 0;
-}
-
-static int gen9_init_render_ring(struct intel_engine_cs *engine)
-{
-	int ret;
-
-	ret = gen8_init_common_ring(engine);
-	if (ret)
-		return ret;
-
-	intel_engine_apply_whitelist(engine);
-
-	return 0;
-}
-
 static struct i915_request *
 execlists_reset_prepare(struct intel_engine_cs *engine)
 {
@@ -2286,10 +2250,6 @@  int logical_render_ring_init(struct intel_engine_cs *engine)
 		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
 	/* Override some for render ring. */
-	if (INTEL_GEN(dev_priv) >= 9)
-		engine->init_hw = gen9_init_render_ring;
-	else
-		engine->init_hw = gen8_init_render_ring;
 	engine->init_context = gen8_init_rcs_context;
 	engine->emit_flush = gen8_emit_flush_render;
 	engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a4ab78bdcbbf..50229eb1eb08 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -1229,6 +1229,20 @@  static void rcs_engine_wa_init(struct intel_engine_cs *engine)
 			    GEN8_L3SQCREG4,
 			    GEN8_LQSC_FLUSH_COHERENT_LINES);
 	}
+
+	if (IS_GEN8(i915)) {
+		/*
+		 * We need to disable the AsyncFlip performance optimisations
+		 * in order to use MI_WAIT_FOR_EVENT within the CS. It should
+		 * already be programmed to '1' on all products.
+		 *
+		 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
+		 */
+		wa_masked_en(wal, MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+
+		/* XXX Is not INSTPM per-context + non-priv for gen6+? */
+		wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
+	}
 }
 
 static void xcs_engine_wa_init(struct intel_engine_cs *engine)

Comments

Tvrtko Ursulin Dec. 6, 2018, 1:02 p.m.
On 06/12/2018 12:56, Chris Wilson wrote:
> We can move the remaining RCS workarounds applied to only gen8 to the
> engine->wa_list, and then reduce all engine->init_hw callbacks to common
> code. The benefit of using the new wa_list is that we verify that the
> registers are indeed restored and keep their magic values.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_lrc.c         | 42 +-----------------------
>   drivers/gpu/drm/i915/intel_workarounds.c | 14 ++++++++
>   2 files changed, 15 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0b64bc38f66f..31f378cf5525 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1671,6 +1671,7 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine)
>   static int gen8_init_common_ring(struct intel_engine_cs *engine)
>   {
>   	intel_engine_apply_workarounds(engine);
> +	intel_engine_apply_whitelist(engine);
>   
>   	intel_mocs_init_engine(engine);
>   
> @@ -1687,43 +1688,6 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
>   	return 0;
>   }
>   
> -static int gen8_init_render_ring(struct intel_engine_cs *engine)
> -{
> -	struct drm_i915_private *dev_priv = engine->i915;
> -	int ret;
> -
> -	ret = gen8_init_common_ring(engine);
> -	if (ret)
> -		return ret;
> -
> -	intel_engine_apply_whitelist(engine);
> -
> -	/* We need to disable the AsyncFlip performance optimisations in order
> -	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
> -	 * programmed to '1' on all products.
> -	 *
> -	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
> -	 */
> -	I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
> -
> -	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
> -
> -	return 0;
> -}
> -
> -static int gen9_init_render_ring(struct intel_engine_cs *engine)
> -{
> -	int ret;
> -
> -	ret = gen8_init_common_ring(engine);
> -	if (ret)
> -		return ret;
> -
> -	intel_engine_apply_whitelist(engine);
> -
> -	return 0;
> -}
> -
>   static struct i915_request *
>   execlists_reset_prepare(struct intel_engine_cs *engine)
>   {
> @@ -2286,10 +2250,6 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
>   		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
>   
>   	/* Override some for render ring. */
> -	if (INTEL_GEN(dev_priv) >= 9)
> -		engine->init_hw = gen9_init_render_ring;
> -	else
> -		engine->init_hw = gen8_init_render_ring;
>   	engine->init_context = gen8_init_rcs_context;
>   	engine->emit_flush = gen8_emit_flush_render;
>   	engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index a4ab78bdcbbf..50229eb1eb08 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -1229,6 +1229,20 @@ static void rcs_engine_wa_init(struct intel_engine_cs *engine)
>   			    GEN8_L3SQCREG4,
>   			    GEN8_LQSC_FLUSH_COHERENT_LINES);
>   	}
> +
> +	if (IS_GEN8(i915)) {
> +		/*
> +		 * We need to disable the AsyncFlip performance optimisations
> +		 * in order to use MI_WAIT_FOR_EVENT within the CS. It should
> +		 * already be programmed to '1' on all products.
> +		 *
> +		 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
> +		 */
> +		wa_masked_en(wal, MI_MODE, ASYNC_FLIP_PERF_DISABLE);
> +
> +		/* XXX Is not INSTPM per-context + non-priv for gen6+? */
> +		wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
> +	}
>   }
>   
>   static void xcs_engine_wa_init(struct intel_engine_cs *engine)
> 

Simples!

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko