[RFC,1/7] drm/i915: Introduce meta framebuffer

Submitted by Zhang, Tina on Dec. 3, 2018, 7:35 a.m.

Details

Message ID 1543822522-3413-2-git-send-email-tina.zhang@intel.com
State New
Series "drm/i915/gvt: Enable vGPU local display direct flip"
Headers show

Commit Message

Zhang, Tina Dec. 3, 2018, 7:35 a.m.
Meta framebuffer, as a special intel_framebuffer, is used to describe
an intel_framebuffer which is already pinned to the GGTT space and can
be accessed by the display engine HW.

In the virtualization world, with the help of GVT-g, vGPUs can share
the entire global GTT space and be able to pin their framebuffers to
the global GTT space. However, vGPUs cannot be able to access the
display HW registers which are fully controlled by host i915.

In order to support the vGPU local display direct flip feature, which
is the vGPU can have several assigned display planes and can post its
framebuffers to those assigned planes, host i915 must program the
display plane registers on behalf of the vGPU. However, without the
knowledge of the vGPU's framebuffers, host i915 cannot program those
plane registers correctly. To fill this gap, the meta framebuffer is
introduced.

The meta framebuffer is used by host i915 to describe the framebuffer
pinned to the GGTT space by guest OS.

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_drv.h    | 15 +++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c | 19 ++++++++++++++++++-
 2 files changed, 33 insertions(+), 1 deletion(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f575ba2..6cf345c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -187,6 +187,12 @@  enum intel_output_type {
 #define INTEL_DSI_VIDEO_MODE	0
 #define INTEL_DSI_COMMAND_MODE	1
 
+
+enum {
+	INTEL_META_FB_VGPU = 1,
+	INTEL_META_FB_MAX,
+};
+
 struct intel_framebuffer {
 	struct drm_framebuffer base;
 	struct intel_rotation_info rot_info;
@@ -200,6 +206,15 @@  struct intel_framebuffer {
 		unsigned int x, y;
 		unsigned int pitch; /* pixels */
 	} rotated[2];
+
+	struct {
+		u32 type_id;
+		u32 ggtt_offset;
+		void *private;
+		void (*update)(struct intel_framebuffer *intel_fb,
+			       enum pipe pipe, enum plane_id plane_id);
+		bool should_be_offscreen;
+	} meta_fb;
 };
 
 struct intel_fbdev {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index abe1938..16a0a5d4 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -486,9 +486,26 @@  skl_program_plane(struct intel_plane *plane,
 	uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 	struct intel_plane *linked = plane_state->linked_plane;
 	const struct drm_framebuffer *fb = plane_state->base.fb;
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	u8 alpha = plane_state->base.alpha >> 8;
 	unsigned long irqflags;
 	u32 keymsk, keymax;
+	u32 offset;
+
+	if (intel_fb->meta_fb.type_id == INTEL_META_FB_VGPU) {
+
+		if (!intel_fb->meta_fb.update)
+			return;
+
+		intel_fb->meta_fb.update(intel_fb, pipe, plane_id);
+
+		if (intel_fb->meta_fb.should_be_offscreen)
+			return;
+
+		offset = intel_fb->meta_fb.ggtt_offset;
+	} else {
+		offset = intel_plane_ggtt_offset(plane_state);
+	}
 
 	/* Sizes are 0 based */
 	src_w--;
@@ -558,7 +575,7 @@  skl_program_plane(struct intel_plane *plane,
 
 	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
 	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
-		      intel_plane_ggtt_offset(plane_state) + surf_addr);
+		      offset + surf_addr);
 
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }

Comments

lab_gvt-test@intel.com Dec. 3, 2018, 7:43 a.m.