[v2,07/11] drm/i915/psr: Check if resolution is supported by default SU granularity

Submitted by José Roberto de Souza on Nov. 30, 2018, 2:25 a.m.

Details

Message ID 20181130022525.25676-7-jose.souza@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in DRI devel

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Commit Message

José Roberto de Souza Nov. 30, 2018, 2:25 a.m.
Selective updates have a default granularity requirements as stated
by eDP spec, so check if HW can match those requirements before
enable PSR2.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

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diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c4a8f476eea9..282ff1bc68a7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -539,6 +539,18 @@  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	/* HW will always send full lines in SU blocks, so X will
+	 * always be 0 and we only need to check the width to validate
+	 * horizontal granularity.
+	 * About vertical granularity HW works by SU blocks starting
+	 * at each 4 lines with height of 4 lines, what eDP states
+	 * that sink should support.
+	 */
+	if (crtc_hdisplay % 4) {
+		DRM_DEBUG_KMS("PSR2 not enabled, default SU granularity not match\n");
+		return false;
+	}
+
 	return true;
 }
 

Comments

On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> Selective updates have a default granularity requirements as stated
> by eDP spec
Needs reference to the location in the spec.

> , so check if HW can match those requirements before
> enable PSR2.
typo: enabling*

> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index c4a8f476eea9..282ff1bc68a7 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -539,6 +539,18 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	/* HW will always send full lines in SU blocks, so X will
s/X/starting X coordinate

> +	 * always be 0 and we only need to check the width to validate
> +	 * horizontal granularity.

> +	 * About vertical granularity HW works by SU blocks starting
> +	 * at each 4 lines with height of 4 lines, what eDP states
> +	 * that sink should support.
How about rewriting this as -  
"HW sends SU blocks of size four scan lines, which means the starting X
coordinate and Y granularity requirements will always be met. We only
need to validate the SU block width is a multiple of 4."?




> +	 */
> +	if (crtc_hdisplay % 4) {
> +		DRM_DEBUG_KMS("PSR2 not enabled, default SU granularity
> not match\n");
"PSR2 not enabled, hdisplay(%d) not multiple of 4\n"

With nits addressed,

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> +		return false;
> +	}
> +
>  	return true;
>  }
>
On Fri, 2018-11-30 at 16:37 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > Selective updates have a default granularity requirements as stated
> > by eDP spec
> Needs reference to the location in the spec.

Done

> 
> > , so check if HW can match those requirements before
> > enable PSR2.
> typo: enabling*

Done

> 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index c4a8f476eea9..282ff1bc68a7 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -539,6 +539,18 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> >  		return false;
> >  	}
> >  
> > +	/* HW will always send full lines in SU blocks, so X will
> s/X/starting X coordinate
> 
> > +	 * always be 0 and we only need to check the width to validate
> > +	 * horizontal granularity.
> > +	 * About vertical granularity HW works by SU blocks starting
> > +	 * at each 4 lines with height of 4 lines, what eDP states
> > +	 * that sink should support.
> How about rewriting this as -  
> "HW sends SU blocks of size four scan lines, which means the starting
> X
> coordinate and Y granularity requirements will always be met. We only
> need to validate the SU block width is a multiple of 4."?
> 
> 

Sounds better, thanks

> 
> 
> > +	 */
> > +	if (crtc_hdisplay % 4) {
> > +		DRM_DEBUG_KMS("PSR2 not enabled, default SU granularity
> > not match\n");
> "PSR2 not enabled, hdisplay(%d) not multiple of 4\n"

Done.

> 
> With nits addressed,
> 
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 

Thanks

> > +		return false;
> > +	}
> > +
> >  	return true;
> >  }
> >