[v6,4/4] drm/i915/fec: Disable FEC state.

Submitted by Srivatsa, Anusha on Nov. 5, 2018, 11:31 p.m.

Details

Message ID 20181105233150.1972-5-anusha.srivatsa@intel.com
State New
Headers show
Series "Forward Error Correction" ( rev: 6 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Srivatsa, Anusha Nov. 5, 2018, 11:31 p.m.
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.

v2:
- rebased.
- Add additional check for compression state. (Gaurav)

v3: rebased.

v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)

v5: Remove unnecessary checks (Ville)

v6: Resolve warnings. Add crtc_state as an argument to
intel_disable_ddi_buf(). (Manasi)

Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 29 +++++++++++++++++++++++++----
 1 file changed, 25 insertions(+), 4 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fad7385dbd76..21af8fe1cf35 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3087,6 +3087,22 @@  static void intel_ddi_enable_fec(struct intel_encoder *encoder,
 		DRM_ERROR("Timed out waiting for FEC Enable Status\n");
 }
 
+static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
+					const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum port port = encoder->port;
+	u32 val;
+
+	if (!crtc_state->fec_enable)
+		return;
+
+	val = I915_READ(DP_TP_CTL(port));
+	val &= ~DP_TP_CTL_FEC_ENABLE;
+	I915_WRITE(DP_TP_CTL(port), val);
+	POSTING_READ(DP_TP_CTL(port));
+}
+
 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state)
@@ -3230,10 +3246,12 @@  static void intel_ddi_pre_enable(struct intel_encoder *encoder,
 	}
 }
 
-static void intel_disable_ddi_buf(struct intel_encoder *encoder)
+static void intel_disable_ddi_buf(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+
 	bool wait = false;
 	u32 val;
 
@@ -3249,6 +3267,9 @@  static void intel_disable_ddi_buf(struct intel_encoder *encoder)
 	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
 	I915_WRITE(DP_TP_CTL(port), val);
 
+	/* Disable FEC in DP Sink */
+	intel_ddi_disable_fec_state(encoder, crtc_state);
+
 	if (wait)
 		intel_wait_ddi_buf_idle(dev_priv, port);
 }
@@ -3272,7 +3293,7 @@  static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
 	}
 
-	intel_disable_ddi_buf(encoder);
+	intel_disable_ddi_buf(encoder, old_crtc_state);
 
 	intel_edp_panel_vdd_on(intel_dp);
 	intel_edp_panel_off(intel_dp);
@@ -3295,7 +3316,7 @@  static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
 
 	intel_ddi_disable_pipe_clock(old_crtc_state);
 
-	intel_disable_ddi_buf(encoder);
+	intel_disable_ddi_buf(encoder, old_crtc_state);
 
 	intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
 
@@ -3346,7 +3367,7 @@  void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
 	val &= ~FDI_RX_ENABLE;
 	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
 
-	intel_disable_ddi_buf(encoder);
+	intel_disable_ddi_buf(encoder, old_crtc_state);
 	intel_ddi_clk_disable(encoder);
 
 	val = I915_READ(FDI_RX_MISC(PIPE_A));

Comments

On Mon, Nov 05, 2018 at 03:31:50PM -0800, Anusha Srivatsa wrote:
> Set the suitable bits in DP_TP_CTL to stop
> bit correction when DSC is disabled.
> 
> v2:
> - rebased.
> - Add additional check for compression state. (Gaurav)
> 
> v3: rebased.
> 
> v4:
> - Move the code to the proper spot according to spec (Ville)
> - Use proper checks (manasi)
> 
> v5: Remove unnecessary checks (Ville)
> 
> v6: Resolve warnings. Add crtc_state as an argument to
> intel_disable_ddi_buf(). (Manasi)
> 
> Cc: dri-devel@lists.freedesktop.org
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 29 +++++++++++++++++++++++++----
>  1 file changed, 25 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index fad7385dbd76..21af8fe1cf35 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3087,6 +3087,22 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
>  		DRM_ERROR("Timed out waiting for FEC Enable Status\n");
>  }
>  
> +static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
> +					const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum port port = encoder->port;
> +	u32 val;
> +
> +	if (!crtc_state->fec_enable)
> +		return;
> +
> +	val = I915_READ(DP_TP_CTL(port));
> +	val &= ~DP_TP_CTL_FEC_ENABLE;
> +	I915_WRITE(DP_TP_CTL(port), val);
> +	POSTING_READ(DP_TP_CTL(port));
> +}
> +
>  static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>  				    const struct intel_crtc_state *crtc_state,
>  				    const struct drm_connector_state *conn_state)
> @@ -3230,10 +3246,12 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder,
>  	}
>  }
>  
> -static void intel_disable_ddi_buf(struct intel_encoder *encoder)
> +static void intel_disable_ddi_buf(struct intel_encoder *encoder,
> +				  const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +

unnecessary change , bogus blank line.
With that fix,

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi


>  	bool wait = false;
>  	u32 val;
>  
> @@ -3249,6 +3267,9 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder)
>  	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
>  	I915_WRITE(DP_TP_CTL(port), val);
>  
> +	/* Disable FEC in DP Sink */
> +	intel_ddi_disable_fec_state(encoder, crtc_state);
> +
>  	if (wait)
>  		intel_wait_ddi_buf_idle(dev_priv, port);
>  }
> @@ -3272,7 +3293,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>  	}
>  
> -	intel_disable_ddi_buf(encoder);
> +	intel_disable_ddi_buf(encoder, old_crtc_state);
>  
>  	intel_edp_panel_vdd_on(intel_dp);
>  	intel_edp_panel_off(intel_dp);
> @@ -3295,7 +3316,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
>  
>  	intel_ddi_disable_pipe_clock(old_crtc_state);
>  
> -	intel_disable_ddi_buf(encoder);
> +	intel_disable_ddi_buf(encoder, old_crtc_state);
>  
>  	intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
>  
> @@ -3346,7 +3367,7 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
>  	val &= ~FDI_RX_ENABLE;
>  	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
>  
> -	intel_disable_ddi_buf(encoder);
> +	intel_disable_ddi_buf(encoder, old_crtc_state);
>  	intel_ddi_clk_disable(encoder);
>  
>  	val = I915_READ(FDI_RX_MISC(PIPE_A));
> -- 
> 2.19.1
>