[v6,1/4] i915/dp/fec: Add fec_enable to the crtc state.

Submitted by Srivatsa, Anusha on Nov. 5, 2018, 11:31 p.m.

Details

Message ID 20181105233150.1972-2-anusha.srivatsa@intel.com
State New
Headers show
Series "Forward Error Correction" ( rev: 6 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Srivatsa, Anusha Nov. 5, 2018, 11:31 p.m.
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.

Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.

v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)

- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)

v3: Check for FEC support along with setting crtc state.

v4: add checks to intel_dp_source_supports_dsc.(manasi)
- Move intel_dp_supports_fec() closer to
intel_dp_supports_dsc() (Anusha)

Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 28 +++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 2 files changed, 28 insertions(+), 3 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 73c00c5acf14..60e323662eea 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -545,7 +545,7 @@  intel_dp_mode_valid(struct drm_connector *connector,
 			dsc_slice_count =
 				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 								true);
-		} else {
+		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 			dsc_max_output_bpp =
 				intel_dp_dsc_get_output_bpp(max_link_clock,
 							    max_lanes,
@@ -1710,13 +1710,27 @@  struct link_config_limits {
 	int min_bpp, max_bpp;
 };
 
+static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	enum port port = dig_port->base.port;
+
+	return INTEL_GEN(dev_priv) >= 11 && port != PORT_A;
+}
+
+static bool intel_dp_supports_fec(struct intel_dp *intel_dp)
+{
+	return intel_dp_source_supports_fec(intel_dp) &&
+		drm_dp_sink_supports_fec(intel_dp->fec_capable);
+}
+
 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
 					 const struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	/* FIXME: FEC needed for external DP until then reject DSC on DP */
-	if (!intel_dp_is_edp(intel_dp))
+	if (!intel_dp_supports_fec(intel_dp) && !intel_dp_is_edp(intel_dp))
 		return false;
 
 	return INTEL_GEN(dev_priv) >= 10 &&
@@ -1886,9 +1900,17 @@  static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	u16 dsc_max_output_bpp = 0;
 	u8 dsc_dp_slice_count = 0;
 
+	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp);
+
 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
 		return false;
 
+	/* DSC not supported if external DP sink does not support FEC */
+	if (pipe_config->fec_enable && !intel_dp_supports_fec(intel_dp)) {
+		DRM_DEBUG_KMS("Sink does not support Forward Error Correction, disabling Display Compression\n");
+		return false;
+	}
+
 	/* DSC not supported for DSC sink BPC < 8 */
 	if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
 		DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index dd22cdeaa673..997bea5fdf16 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -945,6 +945,9 @@  struct intel_crtc_state {
 		u8 slice_count;
 	} dsc_params;
 	struct drm_dsc_config dp_dsc_cfg;
+
+	/* Forward Error correction State */
+	bool fec_enable;
 };
 
 struct intel_crtc {

Comments

On Mon, Nov 05, 2018 at 03:31:47PM -0800, Anusha Srivatsa wrote:
> For DP 1.4 and above, Display Stream compression can be
> enabled only if Forward Error Correctin can be performed.
> 
> Add a crtc state for FEC. Currently, the state
> is determined by platform, DP and DSC being
> enabled. Moving forward we can use the state
> to have error correction on other scenarios too
> if needed.
> 
> v2:
> - Control compression_enable with the fec_enable
> parameter in crtc state and with intel_dp_supports_fec()
> (Ville)
> 
> - intel_dp_can_fec()/intel_dp_supports_fec()(manasi)
> 
> v3: Check for FEC support along with setting crtc state.
> 
> v4: add checks to intel_dp_source_supports_dsc.(manasi)
> - Move intel_dp_supports_fec() closer to
> intel_dp_supports_dsc() (Anusha)
> 
> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 28 +++++++++++++++++++++++++---
>  drivers/gpu/drm/i915/intel_drv.h |  3 +++
>  2 files changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 73c00c5acf14..60e323662eea 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -545,7 +545,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  			dsc_slice_count =
>  				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
>  								true);
> -		} else {
> +		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
>  			dsc_max_output_bpp =
>  				intel_dp_dsc_get_output_bpp(max_link_clock,
>  							    max_lanes,
> @@ -1710,13 +1710,27 @@ struct link_config_limits {
>  	int min_bpp, max_bpp;
>  };
>  
> +static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	enum port port = dig_port->base.port;
> +
> +	return INTEL_GEN(dev_priv) >= 11 && port != PORT_A;
> +}
> +
> +static bool intel_dp_supports_fec(struct intel_dp *intel_dp)
> +{
> +	return intel_dp_source_supports_fec(intel_dp) &&
> +		drm_dp_sink_supports_fec(intel_dp->fec_capable);
> +}
> +
>  static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  					 const struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	/* FIXME: FEC needed for external DP until then reject DSC on DP */
> -	if (!intel_dp_is_edp(intel_dp))
> +	if (!intel_dp_supports_fec(intel_dp) && !intel_dp_is_edp(intel_dp))
>  		return false;
>  
>  	return INTEL_GEN(dev_priv) >= 10 &&
> @@ -1886,9 +1900,17 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	u16 dsc_max_output_bpp = 0;
>  	u8 dsc_dp_slice_count = 0;
>  
> +	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp);

fec_enable state be set based on !intel_dp_is_edp() && intel_dp_supports_fec()
Because we enable fec in atomic ocmmit just based on this crtc_state->fec_enable so
it should definitely be set based on intel_dp_supports_fec()

> +
>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>  		return false;
>  
> +	/* DSC not supported if external DP sink does not support FEC */
> +	if (pipe_config->fec_enable && !intel_dp_supports_fec(intel_dp)) {

Then here just check for if (pipe_config->fec_enable)

Manasi

> +		DRM_DEBUG_KMS("Sink does not support Forward Error Correction, disabling Display Compression\n");
> +		return false;
> +	}
> +
>  	/* DSC not supported for DSC sink BPC < 8 */
>  	if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
>  		DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index dd22cdeaa673..997bea5fdf16 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -945,6 +945,9 @@ struct intel_crtc_state {
>  		u8 slice_count;
>  	} dsc_params;
>  	struct drm_dsc_config dp_dsc_cfg;
> +
> +	/* Forward Error correction State */
> +	bool fec_enable;
>  };
>  
>  struct intel_crtc {
> -- 
> 2.19.1
>
On Mon, Nov 05, 2018 at 03:31:47PM -0800, Anusha Srivatsa wrote:
> For DP 1.4 and above, Display Stream compression can be
> enabled only if Forward Error Correctin can be performed.
> 
> Add a crtc state for FEC. Currently, the state
> is determined by platform, DP and DSC being
> enabled. Moving forward we can use the state
> to have error correction on other scenarios too
> if needed.
> 
> v2:
> - Control compression_enable with the fec_enable
> parameter in crtc state and with intel_dp_supports_fec()
> (Ville)
> 
> - intel_dp_can_fec()/intel_dp_supports_fec()(manasi)
> 
> v3: Check for FEC support along with setting crtc state.
> 
> v4: add checks to intel_dp_source_supports_dsc.(manasi)
> - Move intel_dp_supports_fec() closer to
> intel_dp_supports_dsc() (Anusha)
> 
> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 28 +++++++++++++++++++++++++---
>  drivers/gpu/drm/i915/intel_drv.h |  3 +++
>  2 files changed, 28 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 73c00c5acf14..60e323662eea 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -545,7 +545,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  			dsc_slice_count =
>  				drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
>  								true);
> -		} else {
> +		} else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
>  			dsc_max_output_bpp =
>  				intel_dp_dsc_get_output_bpp(max_link_clock,
>  							    max_lanes,
> @@ -1710,13 +1710,27 @@ struct link_config_limits {
>  	int min_bpp, max_bpp;
>  };
>  
> +static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	enum port port = dig_port->base.port;
> +
> +	return INTEL_GEN(dev_priv) >= 11 && port != PORT_A;
> +}
> +
> +static bool intel_dp_supports_fec(struct intel_dp *intel_dp)
> +{
> +	return intel_dp_source_supports_fec(intel_dp) &&
> +		drm_dp_sink_supports_fec(intel_dp->fec_capable);
> +}
> +
>  static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  					 const struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	/* FIXME: FEC needed for external DP until then reject DSC on DP */
> -	if (!intel_dp_is_edp(intel_dp))
> +	if (!intel_dp_supports_fec(intel_dp) && !intel_dp_is_edp(intel_dp))
>  		return false;

Hmm. I guess we should move this whole check to
intel_dp_supports_dsc() since we're now checking sink caps as well.

>  
>  	return INTEL_GEN(dev_priv) >= 10 &&
> @@ -1886,9 +1900,17 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	u16 dsc_max_output_bpp = 0;
>  	u8 dsc_dp_slice_count = 0;
>  
> +	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp);
> +
>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>  		return false;
>  
> +	/* DSC not supported if external DP sink does not support FEC */
> +	if (pipe_config->fec_enable && !intel_dp_supports_fec(intel_dp)) {
> +		DRM_DEBUG_KMS("Sink does not support Forward Error Correction, disabling Display Compression\n");
> +		return false;
> +	}
> +
>  	/* DSC not supported for DSC sink BPC < 8 */
>  	if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
>  		DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index dd22cdeaa673..997bea5fdf16 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -945,6 +945,9 @@ struct intel_crtc_state {
>  		u8 slice_count;
>  	} dsc_params;
>  	struct drm_dsc_config dp_dsc_cfg;
> +
> +	/* Forward Error correction State */
> +	bool fec_enable;
>  };
>  
>  struct intel_crtc {
> -- 
> 2.19.1