[v1,4/5] drm/i915/gvt: GVTg support master irq pvmmio optimization

Submitted by Zhang, Xiaolin on Nov. 5, 2018, 9:20 a.m.

Details

Message ID 1541409649-21171-4-git-send-email-xiaolin.zhang@intel.com
State New
Series "Series without cover letter"
Headers show

Commit Message

Zhang, Xiaolin Nov. 5, 2018, 9:20 a.m.
GVTg to check master irq status in the shared_page instead
of register.

v1: rebase
v0: RFC

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Min He<min.he@intel.com>
Cc: Fei Jiang <fei.jiang@intel.com>
Cc: Zhipeng Gong <zhipeng.gong@intel.com>
Cc: Hang Yuan <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c  |  4 ++++
 drivers/gpu/drm/i915/gvt/interrupt.c | 17 +++++++++++++----
 2 files changed, 17 insertions(+), 4 deletions(-)

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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index cd3b602..d6572cd 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1231,6 +1231,7 @@  static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 {
 	u32 data;
 	int ret;
+	struct intel_gvt_irq_ops *ops = vgpu->gvt->irq.ops;
 
 	write_vreg(vgpu, offset, p_data, bytes);
 	data = vgpu_vreg(vgpu, offset);
@@ -1257,6 +1258,9 @@  static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		vgpu->shared_page_gpa = vgpu_vreg64_t(vgpu,
 			vgtif_reg(shared_page_gpa));
 		break;
+	case _vgtif_reg(check_pending_irq):
+		ops->check_pending_irq(vgpu);
+		break;
 	/* add xhot and yhot to handled list to avoid error log */
 	case _vgtif_reg(cursor_x_hot):
 	case _vgtif_reg(cursor_y_hot):
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 5daa23a..c1884f8 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -465,10 +465,19 @@  static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
 {
 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
 	int i;
-
-	if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
-				GEN8_MASTER_IRQ_CONTROL))
-		return;
+	u32 offset;
+	u32 disable_irq;
+
+	if (VGPU_PVMMIO(vgpu) & PVMMIO_MASTER_IRQ) {
+		offset = offsetof(struct gvt_shared_page, disable_irq);
+		intel_gvt_read_shared_page(vgpu, offset, &disable_irq, 4);
+		if (disable_irq)
+			return;
+	} else {
+		if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
+		       GEN8_MASTER_IRQ_CONTROL))
+			return;
+	}
 
 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
 		struct intel_gvt_irq_info *info = irq->info[i];