[v9,11/15] drm/i915/icl: Define Panel power ctrl register

Submitted by Jani Nikula on Nov. 1, 2018, 3:34 p.m.

Details

Message ID b0ecc76ac5b19dbb20c1ccf1b17f9d37ae969acf.1541086315.git.jani.nikula@intel.com
State New
Headers show
Series "drm/i915/icl: dsi enabling" ( rev: 4 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Jani Nikula Nov. 1, 2018, 3:34 p.m.
From: Madhav Chauhan <madhav.chauhan@intel.com>

There are two panel power sequencers. Each register
has two addressable instances. This patch defines
both the instances of Panel power control register

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d58a9ff4f76..dbd8eef8aa8c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4596,6 +4596,17 @@  enum {
 #define _PP_STATUS			0x61200
 #define PP_STATUS(pps_idx)		_MMIO_PPS(pps_idx, _PP_STATUS)
 #define   PP_ON				(1 << 31)
+
+#define _PP_CONTROL_1			0xc7204
+#define _PP_CONTROL_2			0xc7304
+#define ICP_PP_CONTROL(x)		_MMIO(((x) == 1) ? _PP_CONTROL_1 : \
+					      _PP_CONTROL_2)
+#define  POWER_CYCLE_DELAY_MASK	(0x1f << 4)
+#define  POWER_CYCLE_DELAY_SHIFT	4
+#define  VDD_OVERRIDE_FORCE		(1 << 3)
+#define  BACKLIGHT_ENABLE		(1 << 2)
+#define  PWR_DOWN_ON_RESET		(1 << 1)
+#define  PWR_STATE_TARGET		(1 << 0)
 /*
  * Indicates that all dependencies of the panel are on:
  *