[v2,2/3] drm/msm: dpu: Only check flush register against pending flushes

Submitted by Sean Paul on Oct. 30, 2018, 4 p.m.

Details

Message ID 20181030160033.18464-2-sean@poorly.run
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Freedreno

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Commit Message

Sean Paul Oct. 30, 2018, 4 p.m.
From: Sean Paul <seanpaul@chromium.org>

There exists a case where a flush of a plane/dma may have been triggered
& started from an async commit. If that plane/dma is subsequently disabled
by the next commit, the flush register will continue to hold the flush
bit for the disabled plane. Since the bit remains active,
pending_kickoff_cnt will never decrement and we'll miss frame_done
events.

This patch limits the check of flush_register to include only those bits
which have been updated with the latest commit.

Changes in v2:
- None

Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

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diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index b3c68c4fcc8e..667f304c92ea 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -331,7 +331,7 @@  static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx)
 	if (hw_ctl && hw_ctl->ops.get_flush_register)
 		flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
 
-	if (flush_register == 0)
+	if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
 		new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt,
 				-1, 0);
 	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);

Comments

On 2018-10-30 09:00, Sean Paul wrote:
> From: Sean Paul <seanpaul@chromium.org>
> 
> There exists a case where a flush of a plane/dma may have been 
> triggered
> & started from an async commit. If that plane/dma is subsequently 
> disabled
> by the next commit, the flush register will continue to hold the flush
> bit for the disabled plane. Since the bit remains active,
> pending_kickoff_cnt will never decrement and we'll miss frame_done
> events.
> 
> This patch limits the check of flush_register to include only those 
> bits
> which have been updated with the latest commit.
> 
> Changes in v2:
> - None
> 

Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org>

> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index b3c68c4fcc8e..667f304c92ea 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -331,7 +331,7 @@ static void dpu_encoder_phys_vid_vblank_irq(void 
> *arg,
> int irq_idx)
>  	if (hw_ctl && hw_ctl->ops.get_flush_register)
>  		flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
> 
> -	if (flush_register == 0)
> +	if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
>  		new_cnt =
> atomic_add_unless(&phys_enc->pending_kickoff_cnt,
>  				-1, 0);
>  	spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);