[v8,23/38] drm/i915/icl: Add get config functionality for DSI

Submitted by Jani Nikula on Oct. 30, 2018, 11:56 a.m.

Details

Message ID 6ddb2b8dfe50acc7e44b08292ff7ce704e14e63f.1540900289.git.jani.nikula@intel.com
State New
Headers show
Series "drm/i915/icl: dsi enabling" ( rev: 3 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Jani Nikula Oct. 30, 2018, 11:56 a.m.
From: Madhav Chauhan <madhav.chauhan@intel.com>

This patch implements the functionality for getting PIPE
configuration to which DSI encoder is connected. Used during
the atomic modeset.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

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diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 58774a1ac84b..83612c444eab 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1054,6 +1054,19 @@  static void gen11_dsi_disable(struct intel_encoder *encoder,
 	gen11_dsi_disable_io_power(encoder);
 }
 
+static void gen11_dsi_get_config(struct intel_encoder *encoder,
+				 struct intel_crtc_state *pipe_config)
+{
+	struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+						   base);
+	u32 pixel_clk;
+
+	//FIXME: Calculate pixel clock using PLL functions once implemented.
+	pixel_clk = intel_dsi->pclk;
+	pipe_config->base.adjusted_mode.crtc_clock = pixel_clk;
+	pipe_config->port_clock = pixel_clk;
+}
+
 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
 {
 	intel_encoder_destroy(encoder);
@@ -1152,6 +1165,7 @@  void icl_dsi_init(struct drm_i915_private *dev_priv)
 	encoder->pre_enable = gen11_dsi_pre_enable;
 	encoder->disable = gen11_dsi_disable;
 	encoder->port = port;
+	encoder->get_config = gen11_dsi_get_config;
 	encoder->type = INTEL_OUTPUT_DSI;
 	encoder->cloneable = 0;
 	encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);