[v2] drm/i915/gvt: not to touch undefined MOCS registers

Submitted by Xinyun Liu on Oct. 29, 2018, 6:18 a.m.

Details

Message ID 20181029061825.15484-1-xinyun.liu@intel.com
State New
Series "drm/i915/gvt: not to touch undefined registers"
Headers show

Commit Message

Xinyun Liu Oct. 29, 2018, 6:18 a.m.
Some engines are not available for all Gens. eg, Gen11 introduced
VCS3/VCS4/VECS2, and VCS2 is not supported on some Gen9 machines. So need to
add check before access them. 

Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
Signed-off-by: Yakui Zhao <Yakui.Zhao@intel.com>
---
 drivers/gpu/drm/i915/gvt/mmio_context.c | 2 ++
 1 file changed, 2 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index e872f4847fbe..2693de36c557 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -171,6 +171,8 @@  static void load_render_mocs(struct drm_i915_private *dev_priv)
 	int ring_id, i;
 
 	for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
+		if (!HAS_ENGINE(dev_priv, ring_id))
+			continue;
 		offset.reg = regs[ring_id];
 		for (i = 0; i < GEN9_MOCS_SIZE; i++) {
 			gen9_render_mocs.control_table[ring_id][i] =

Comments

gvt@intel.com Oct. 29, 2018, 9:37 a.m.

Zhenyu Wang Nov. 12, 2018, 9:01 a.m.
On 2018.10.29 14:18:25 +0800, Xinyun Liu wrote:
> Some engines are not available for all Gens. eg, Gen11 introduced
> VCS3/VCS4/VECS2, and VCS2 is not supported on some Gen9 machines. So need to
> add check before access them. 
> 
> Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
> Signed-off-by: Yakui Zhao <Yakui.Zhao@intel.com>
> ---

Applied! Sorry for the delay.