[v2,5/5] drm/i915: ppgtt update pvmmio optimization

Submitted by Zhang, Xiaolin on Oct. 19, 2018, 7:27 a.m.

Details

Message ID 1539934034-31343-6-git-send-email-xiaolin.zhang@intel.com
State New
Series "i915 pvmmio to improve GVTg performance"
Headers show

Commit Message

Zhang, Xiaolin Oct. 19, 2018, 7:27 a.m.
This patch extends g2v notification to notify host GVT-g of
ppgtt update from guest, including alloc_4lvl, clear_4lv4 and
insert_4lvl. It uses shared page to pass the additional params.
This patch also add one new pvmmio level to control ppgtt update.

Use PVMMIO_PPGTT_UPDATE to control this level of pvmmio optimization.

v0: RFC
v1: rebase
v2: added pv callbacks for vm.{allocate_va_range, insert_entries,
clear_range} within ppgtt.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 67 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_pvinfo.h  |  3 ++
 drivers/gpu/drm/i915/i915_vgpu.c    |  3 +-
 3 files changed, 72 insertions(+), 1 deletion(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 98d9a1e..b529f53 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -956,6 +956,25 @@  static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
 	}
 }
 
+static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
+				  u64 start, u64 length)
+{
+	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+	struct i915_pml4 *pml4 = &ppgtt->pml4;
+	struct drm_i915_private *dev_priv = vm->i915;
+	struct pv_ppgtt_update *pv_ppgtt =
+			&dev_priv->vgpu.shared_page->pv_ppgtt;
+	u64 orig_start = start;
+	u64 orig_length = length;
+
+	gen8_ppgtt_clear_4lvl(vm, start, length);
+
+	pv_ppgtt->pdp = px_dma(pml4);
+	pv_ppgtt->start = orig_start;
+	pv_ppgtt->length = orig_length;
+	I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
+}
+
 static inline struct sgt_dma {
 	struct scatterlist *sg;
 	dma_addr_t dma, max;
@@ -1197,6 +1216,25 @@  static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
 	}
 }
 
+static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
+				   struct i915_vma *vma,
+				   enum i915_cache_level cache_level,
+				   u32 flags)
+{
+	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+	struct drm_i915_private *dev_priv = vm->i915;
+	struct pv_ppgtt_update *pv_ppgtt =
+			&dev_priv->vgpu.shared_page->pv_ppgtt;
+
+	gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags);
+
+	pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
+	pv_ppgtt->start = vma->node.start;
+	pv_ppgtt->length = vma->node.size;
+	pv_ppgtt->cache_level = cache_level;
+	I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
+}
+
 static void gen8_free_page_tables(struct i915_address_space *vm,
 				  struct i915_page_directory *pd)
 {
@@ -1466,6 +1504,30 @@  static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
 	return -ENOMEM;
 }
 
+static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm,
+				 u64 start, u64 length)
+{
+	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+	struct i915_pml4 *pml4 = &ppgtt->pml4;
+	struct drm_i915_private *dev_priv = vm->i915;
+	struct pv_ppgtt_update *pv_ppgtt =
+			&dev_priv->vgpu.shared_page->pv_ppgtt;
+	int ret;
+	u64 orig_start = start;
+	u64 orig_length = length;
+
+	ret = gen8_ppgtt_alloc_4lvl(vm, start, length);
+	if (ret)
+		return ret;
+
+	pv_ppgtt->pdp = px_dma(pml4);
+	pv_ppgtt->start = orig_start;
+	pv_ppgtt->length = orig_length;
+	I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_ALLOC);
+
+	return 0;
+}
+
 static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt,
 			  struct i915_page_directory_pointer *pdp,
 			  u64 start, u64 length,
@@ -1631,6 +1693,11 @@  static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
 		ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
+		if (PVMMIO_LEVEL_ENABLE(i915, PVMMIO_PPGTT_UPDATE)) {
+			ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl_pv;
+			ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl_pv;
+			ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl_pv;
+		}
 	} else {
 		err = __pdp_init(&ppgtt->vm, &ppgtt->pdp);
 		if (err)
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 1e24c45..790db50 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,9 @@  enum vgt_g2v_type {
 	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
 	VGT_G2V_EXECLIST_CONTEXT_CREATE,
 	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+	VGT_G2V_PPGTT_L4_ALLOC,
+	VGT_G2V_PPGTT_L4_CLEAR,
+	VGT_G2V_PPGTT_L4_INSERT,
 	VGT_G2V_MAX,
 };
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 013d329..e11dcd8 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,7 +66,8 @@  void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
-	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ;
+	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT
+			| PVMMIO_MASTER_IRQ | PVMMIO_PPGTT_UPDATE;
 
 	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)

Comments

gvt@intel.com Oct. 19, 2018, 4:41 p.m.