[v2] drm/i915/gvt: update force-to-nonpriv register whitelist

Submitted by Zhao, Yan Y on Sept. 17, 2018, 5:56 a.m.

Details

Message ID 20180917055651.27960-1-yan.y.zhao@intel.com
State New
Headers show
Series "drm/i915/gvt: update force-to-nonpriv register whitelist" ( rev: 2 ) in Intel GVT devel

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Commit Message

Zhao, Yan Y Sept. 17, 2018, 5:56 a.m.
Host print below warning message when creating guest:
"gvt: vgpu(2) Invalid FORCE_NONPRIV write 83a8".

Register 0x83a8 should be in force-to-nonpriv whitelist as required by
guest

v2: update commit message to describe purpose of this patch in detail
(zhenyu wang)

Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 1 +
 1 file changed, 1 insertion(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 290e52b1436a..bdeece7d6558 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -449,6 +449,7 @@  static i915_reg_t force_nonpriv_white_list[] = {
 	_MMIO(0x7704),
 	_MMIO(0x7708),
 	_MMIO(0x770c),
+	_MMIO(0x83a8),
 	_MMIO(0xb110),
 	GEN8_L3SQCREG4,//_MMIO(0xb118)
 	_MMIO(0xe100),

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