drm/i915: compile only for GEN2 i830 gpu

Submitted by Andi Shyti on Sept. 14, 2018, 4:13 p.m.

Details

Message ID 20180914161342.22383-1-andi.shyti@intel.com
State New
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Series "drm/i915: compile only for GEN2 i830 gpu" ( rev: 1 ) in Intel GFX - Try Bot

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Commit Message

Andi Shyti Sept. 14, 2018, 4:13 p.m.
---
 drivers/gpu/drm/i915/Kconfig     |   8 +-
 drivers/gpu/drm/i915/Kconfig.sel | 285 +++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h  |  87 +++++-----
 drivers/gpu/drm/i915/i915_pci.c  | 134 +++++++++++++++
 4 files changed, 473 insertions(+), 41 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/Kconfig.sel

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 33a458b7f1fc..9e6cdf066675 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -28,8 +28,7 @@  config DRM_I915
 	help
 	  Choose this option if you have a system that has "Intel Graphics
 	  Media Accelerator" or "HD Graphics" integrated graphics,
-	  including 830M, 845G, 852GM, 855GM, 865G, 915G, 945G, 965G,
-	  G35, G41, G43, G45 chipsets and Celeron, Pentium, Core i3,
+	  including G41, G43, chipsets and Celeron, Pentium, Core i3,
 	  Core i5, Core i7 as well as Atom CPUs with integrated graphics.
 
 	  This driver is used by the Intel driver in X.org 6.8 and
@@ -128,6 +127,11 @@  config DRM_I915_GVT_KVMGT
 	  Choose this option if you want to enable KVMGT support for
 	  Intel GVT-g.
 
+menu "Selective selection"
+depends on DRM_I915
+source drivers/gpu/drm/i915/Kconfig.sel
+endmenu
+
 menu "drm/i915 Debugging"
 depends on DRM_I915
 depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Kconfig.sel b/drivers/gpu/drm/i915/Kconfig.sel
new file mode 100644
index 000000000000..c15e8fa97557
--- /dev/null
+++ b/drivers/gpu/drm/i915/Kconfig.sel
@@ -0,0 +1,285 @@ 
+comment "Intel GEN2"
+
+config DRM_INTEL_GEN2
+	bool
+
+config DRM_INTEL_I830
+	bool "Intel i830 GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN2
+	help
+	  Choose this option if you have an i830 gpu
+
+config DRM_INTEL_I845G
+	bool "Intel i845G GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN2
+	help
+	  Choose this option if you have an i845G gpu
+
+config DRM_INTEL_I85X
+	bool "Intel i85X GPU series"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN2
+	help
+	  Choose this option if you have an i85x gpu series
+
+config DRM_INTEL_I865G
+	bool "Intel i865G GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN2
+	help
+	  Choose this option if you have an i865G gpu
+
+comment "Intel GEN3"
+
+config DRM_INTEL_GEN3
+	bool
+
+config DRM_INTEL_I915G
+	bool "Intel i915G GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN3
+	help
+	  Choose this option if you have an i915G gpu
+
+config DRM_INTEL_I915GM
+	bool "Intel i915GM GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN3
+	help
+	  Choose this option if you have an i915GM gpu
+
+config DRM_INTEL_I945G
+	bool "Intel i945G GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN3
+	help
+	  Choose this option if you have an i945G gpu
+
+config DRM_INTEL_I945GM
+	bool "Intel i945GM GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN3
+	help
+	  Choose this option if you have an i945GM gpu
+
+config DRM_INTEL_G33
+	bool "Intel G33 GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN3
+	help
+	  Choose this option if you have an G33 gpu
+
+config DRM_INTEL_PINEVIEW
+	bool "Intel Pine View GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN3
+	help
+	  Choose this option if you have an Pine View gpu
+
+comment "Intel GEN4"
+
+config DRM_INTEL_GEN4
+	bool
+
+config DRM_INTEL_I965G
+	bool "Intel i965G GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN4
+	help
+	  Choose this option if you have an i965G gpu
+
+config DRM_INTEL_I965GM
+	bool "Intel i965GM GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN4
+	help
+	  Choose this option if you have an i965GM gpu
+
+config DRM_INTEL_G45
+	bool "Intel G45 GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN4
+	help
+	  Choose this option if you have an G45 gpu
+
+config DRM_INTEL_GM45
+	bool "Intel GM45 GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN4
+	help
+	  Choose this option if you have an GM45 gpu
+
+comment "Intel GEN5"
+
+config DRM_INTEL_GEN5
+	bool
+
+config DRM_INTEL_IRONLAKE
+	bool "Intel Iron Lake GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN5
+	help
+	  Choose this option if you have an Iron Lake gpu
+
+comment "Intel GEN6"
+
+config DRM_INTEL_GEN6
+	bool
+
+config DRM_INTEL_SANDYBRIDGE
+	bool "Intel Sandy Bridge GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN6
+	help
+	  Choose this option if you have a Sandy Bridge gpu
+
+comment "Intel GEN7"
+
+config DRM_INTEL_GEN7
+	bool
+
+config DRM_INTEL_IVYBRIDGE
+	bool "Intel Ivy Bridge GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN7
+	help
+	  Choose this option if you have an Ivy Bridge gpu
+
+config DRM_INTEL_VALLEYVIEW
+	bool "Intel Valley View GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN7
+	help
+	  Choose this option if you have a Valley View gpu
+
+comment "Intel GEN7.5"
+
+config DRM_INTEL_GEN75
+	bool
+	select DRM_INTEL_GEN7
+
+config DRM_INTEL_HASWELL
+	bool "Intel Haswell GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN75
+	help
+	  Choose this option if you have a Haswell gpu
+
+# this is temporary to avoid GEN8 compilation error
+
+comment "Intel GEN8"
+
+config DRM_INTEL_GEN8
+	bool
+	select DRM_INTEL_GEN75
+
+config DRM_INTEL_BROADWELL
+	bool "Intel Broadwell GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN8
+	help
+	  Choose this option if you have a Broadwell gpu
+
+config DRM_INTEL_CHERRYVIEW
+	bool "Intel Cherry View GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN8
+	help
+	  Choose this option if you have a Cherry View gpu
+
+comment "Intel GEN9"
+
+config DRM_INTEL_GEN9
+	bool
+	select DRM_INTEL_GEN8
+
+config DRM_INTEL_SKYLAKE
+	bool "Intel Sky Lake GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Sky Lake gpu
+
+config DRM_INTEL_BROXTON
+	bool "Intel Broxton GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Broxton gpu
+
+config DRM_INTEL_KABYLAKE
+	bool "Intel Kaby Lake GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Kaby Lake gpu
+
+config DRM_INTEL_GEMINILAKE
+	bool "Intel Gemini Lake GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Gemini Lake gpu
+
+config DRM_INTEL_COFFEELAKE
+	bool "Intel Coffee Lake GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Coffee Lake gpu
+
+comment "Intel GEN10"
+
+config DRM_INTEL_GEN10
+	bool
+	select DRM_INTEL_GEN9
+
+config DRM_INTEL_CANNONLAKE
+	bool "Intel Cannon Lake GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN10
+	help
+	  Choose this option if you have a Cannon Lake gpu
+
+comment "Intel GEN11"
+
+config DRM_INTEL_GEN11
+	bool
+	select DRM_INTEL_GEN10
+
+config DRM_INTEL_ICELAKE
+	bool "Intel Ice Lake GPU"
+	default n
+	depends on DRM_I915
+	select DRM_INTEL_GEN11
+	help
+	  Choose this option if you have an Ice Lake gpu
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d4daa7412f1..40f5da786781 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2395,38 +2395,44 @@  intel_info(const struct drm_i915_private *dev_priv)
 
 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
 
-#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
-#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
-#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
-#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
-#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
-#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
-#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
-#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
-#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
-#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
-#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
-#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
+#define IS_SELECTED_PLATFORM(dev_priv, s) \
+	(IS_PLATFORM(dev_priv, s) && IS_ENABLED(CONFIG_DRM_##s))
+
+#define IS_SELECTED_ID(dev_priv, s, id) \
+	(IS_SELECTED_PLATFORM(dev_priv, s) && (INTEL_DEVID(dev_priv) == id))
+
+#define IS_I830(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I830)
+#define IS_I845G(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I845G)
+#define IS_I85X(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I85X)
+#define IS_I865G(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I865G)
+#define IS_I915G(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I915G)
+#define IS_I915GM(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I915GM)
+#define IS_I945G(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I945G)
+#define IS_I945GM(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I945GM)
+#define IS_I965G(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I965G)
+#define IS_I965GM(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I965GM)
+#define IS_G45(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_G45)
+#define IS_GM45(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_GM45)
 #define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
-#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
-#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
-#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
-#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
-#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
-#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
+#define IS_PINEVIEW_G(dev_priv)	IS_SELECTED_ID(dev_priv, INTEL_PINEVIEW, 0xa001)
+#define IS_PINEVIEW_M(dev_priv)	IS_SELECTED_ID(dev_priv, INTEL_PINEVIEW, 0xa011)
+#define IS_PINEVIEW(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_PINEVIEW)
+#define IS_G33(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_G33)
+#define IS_IRONLAKE_M(dev_priv)	IS_SELECTED_ID(dev_priv, INTEL_IRONLAKE, 0x0046)
+#define IS_IVYBRIDGE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
 				 (dev_priv)->info.gt == 1)
-#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
-#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
-#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
-#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
-#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
-#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
-#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
-#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
-#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
-#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
-#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
+#define IS_VALLEYVIEW(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
+#define IS_CHERRYVIEW(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
+#define IS_HASWELL(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_HASWELL)
+#define IS_BROADWELL(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_BROADWELL)
+#define IS_SKYLAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_SKYLAKE)
+#define IS_BROXTON(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_BROXTON)
+#define IS_KABYLAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_KABYLAKE)
+#define IS_GEMINILAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_GEMINILAKE)
+#define IS_COFFEELAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_COFFEELAKE)
+#define IS_CANNONLAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_CANNONLAKE)
+#define IS_ICELAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
@@ -2540,16 +2546,19 @@  intel_info(const struct drm_i915_private *dev_priv)
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
-#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
-#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
-#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
-#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
-#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
-#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
-#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
-#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
-#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
+#define __IS_GEN_X(N, dev_priv) (!!((dev_priv)->info.gen_mask & BIT(N-1)) && \
+				IS_ENABLED(CONFIG_DRIM_I915_GEN##N))
+
+#define IS_GEN2(dev_priv)	__IS_GEN_X(2, dev_priv)
+#define IS_GEN3(dev_priv)	__IS_GEN_X(3, dev_priv)
+#define IS_GEN4(dev_priv)	__IS_GEN_X(4, dev_priv)
+#define IS_GEN5(dev_priv)	__IS_GEN_X(5, dev_priv)
+#define IS_GEN6(dev_priv)	__IS_GEN_X(6, dev_priv)
+#define IS_GEN7(dev_priv)	__IS_GEN_X(7, dev_priv)
+#define IS_GEN8(dev_priv)	__IS_GEN_X(8, dev_priv)
+#define IS_GEN9(dev_priv)	__IS_GEN_X(9, dev_priv)
+#define IS_GEN10(dev_priv)	__IS_GEN_X(10, dev_priv)
+#define IS_GEN11(dev_priv)	__IS_GEN_X(11, dev_priv)
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..730b016cdeb5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -65,6 +65,7 @@ 
 #define GEN_DEFAULT_PAGE_SIZES \
 	.page_sizes = I915_GTT_PAGE_SIZE_4K
 
+#ifdef CONFIG_DRM_INTEL_GEN2
 #define GEN2_FEATURES \
 	GEN(2), \
 	.num_pipes = 1, \
@@ -78,19 +79,25 @@ 
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I830
 static const struct intel_device_info intel_i830_info = {
 	GEN2_FEATURES,
 	PLATFORM(INTEL_I830),
 	.is_mobile = 1, .cursor_needs_physical = 1,
 	.num_pipes = 2, /* legal, last one wins */
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I845
 static const struct intel_device_info intel_i845g_info = {
 	GEN2_FEATURES,
 	PLATFORM(INTEL_I845G),
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I85X
 static const struct intel_device_info intel_i85x_info = {
 	GEN2_FEATURES,
 	PLATFORM(INTEL_I85X),
@@ -99,12 +106,16 @@  static const struct intel_device_info intel_i85x_info = {
 	.cursor_needs_physical = 1,
 	.has_fbc = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I865G
 static const struct intel_device_info intel_i865g_info = {
 	GEN2_FEATURES,
 	PLATFORM(INTEL_I865G),
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN3
 #define GEN3_FEATURES \
 	GEN(3), \
 	.num_pipes = 2, \
@@ -115,7 +126,9 @@  static const struct intel_device_info intel_i865g_info = {
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I915G
 static const struct intel_device_info intel_i915g_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I915G),
@@ -125,7 +138,9 @@  static const struct intel_device_info intel_i915g_info = {
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I915GM
 static const struct intel_device_info intel_i915gm_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I915GM),
@@ -137,7 +152,9 @@  static const struct intel_device_info intel_i915gm_info = {
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I945G
 static const struct intel_device_info intel_i945g_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I945G),
@@ -146,7 +163,9 @@  static const struct intel_device_info intel_i945g_info = {
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I945GM
 static const struct intel_device_info intel_i945gm_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_I945GM),
@@ -158,14 +177,18 @@  static const struct intel_device_info intel_i945gm_info = {
 	.hws_needs_physical = 1,
 	.unfenced_needs_alignment = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_G33
 static const struct intel_device_info intel_g33_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_G33),
 	.has_hotplug = 1,
 	.has_overlay = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_PINEVIEW
 static const struct intel_device_info intel_pineview_info = {
 	GEN3_FEATURES,
 	PLATFORM(INTEL_PINEVIEW),
@@ -173,7 +196,9 @@  static const struct intel_device_info intel_pineview_info = {
 	.has_hotplug = 1,
 	.has_overlay = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN4
 #define GEN4_FEATURES \
 	GEN(4), \
 	.num_pipes = 2, \
@@ -185,7 +210,9 @@  static const struct intel_device_info intel_pineview_info = {
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I965G
 static const struct intel_device_info intel_i965g_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_I965G),
@@ -193,7 +220,9 @@  static const struct intel_device_info intel_i965g_info = {
 	.hws_needs_physical = 1,
 	.has_snoop = false,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I965GM
 static const struct intel_device_info intel_i965gm_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_I965GM),
@@ -203,13 +232,17 @@  static const struct intel_device_info intel_i965gm_info = {
 	.hws_needs_physical = 1,
 	.has_snoop = false,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_G45
 static const struct intel_device_info intel_g45_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_G45),
 	.ring_mask = RENDER_RING | BSD_RING,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GM45
 static const struct intel_device_info intel_gm45_info = {
 	GEN4_FEATURES,
 	PLATFORM(INTEL_GM45),
@@ -217,7 +250,9 @@  static const struct intel_device_info intel_gm45_info = {
 	.supports_tv = 1,
 	.ring_mask = RENDER_RING | BSD_RING,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_IRONLAKE
 #define GEN5_FEATURES \
 	GEN(5), \
 	.num_pipes = 2, \
@@ -241,7 +276,9 @@  static const struct intel_device_info intel_ironlake_m_info = {
 	PLATFORM(INTEL_IRONLAKE),
 	.is_mobile = 1, .has_fbc = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN6
 #define GEN6_FEATURES \
 	GEN(6), \
 	.num_pipes = 2, \
@@ -256,7 +293,9 @@  static const struct intel_device_info intel_ironlake_m_info = {
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
+#endif
 
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
 #define SNB_D_PLATFORM \
 	GEN6_FEATURES, \
 	PLATFORM(INTEL_SANDYBRIDGE)
@@ -286,7 +325,9 @@  static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	SNB_M_PLATFORM,
 	.gt = 2,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN7
 #define GEN7_FEATURES  \
 	GEN(7), \
 	.num_pipes = 3, \
@@ -302,7 +343,9 @@  static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
+#endif
 
+#ifdef CONDFIG_DRM_INTEL_IVYBRIDGE
 #define IVB_D_PLATFORM \
 	GEN7_FEATURES, \
 	PLATFORM(INTEL_IVYBRIDGE), \
@@ -341,7 +384,9 @@  static const struct intel_device_info intel_ivybridge_q_info = {
 	.num_pipes = 0, /* legal, last one wins */
 	.has_l3_dpf = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_VALLEYVIEW
 static const struct intel_device_info intel_valleyview_info = {
 	PLATFORM(INTEL_VALLEYVIEW),
 	GEN(7),
@@ -361,7 +406,9 @@  static const struct intel_device_info intel_valleyview_info = {
 	GEN_DEFAULT_PIPEOFFSETS,
 	CURSOR_OFFSETS
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN75
 #define G75_FEATURES  \
 	GEN7_FEATURES, \
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
@@ -371,7 +418,9 @@  static const struct intel_device_info intel_valleyview_info = {
 	.has_dp_mst = 1, \
 	.has_rc6p = 0 /* RC6p removed-by HSW */, \
 	.has_runtime_pm = 1
+#endif
 
+#ifdef CONFIG_DRM_INTEL_HASWELL
 #define HSW_PLATFORM \
 	G75_FEATURES, \
 	PLATFORM(INTEL_HASWELL), \
@@ -391,7 +440,9 @@  static const struct intel_device_info intel_haswell_gt3_info = {
 	HSW_PLATFORM,
 	.gt = 3,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN8
 #define GEN8_FEATURES \
 	G75_FEATURES, \
 	GEN(8), \
@@ -406,7 +457,9 @@  static const struct intel_device_info intel_haswell_gt3_info = {
 #define BDW_PLATFORM \
 	GEN8_FEATURES, \
 	PLATFORM(INTEL_BROADWELL)
+#endif
 
+#ifdef CONFIG_DRM_INTEL_BROADWELL
 static const struct intel_device_info intel_broadwell_gt1_info = {
 	BDW_PLATFORM,
 	.gt = 1,
@@ -430,7 +483,9 @@  static const struct intel_device_info intel_broadwell_gt3_info = {
 	.gt = 3,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_CHERRYVIEW
 static const struct intel_device_info intel_cherryview_info = {
 	PLATFORM(INTEL_CHERRYVIEW),
 	GEN(8),
@@ -454,7 +509,9 @@  static const struct intel_device_info intel_cherryview_info = {
 	CURSOR_OFFSETS,
 	CHV_COLORS,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN9
 #define GEN9_DEFAULT_PAGE_SIZES \
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_64K | \
@@ -469,7 +526,9 @@  static const struct intel_device_info intel_cherryview_info = {
 	.has_guc = 1, \
 	.has_ipc = 1, \
 	.ddb_size = 896
+#endif
 
+#ifdef CONFIG_DRM_INTEL_SKYLAKE
 #define SKL_PLATFORM \
 	GEN9_FEATURES, \
 	PLATFORM(INTEL_SKYLAKE)
@@ -498,7 +557,9 @@  static const struct intel_device_info intel_skylake_gt4_info = {
 	SKL_GT3_PLUS_PLATFORM,
 	.gt = 4,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN9
 #define GEN9_LP_FEATURES \
 	GEN(9), \
 	.is_lp = 1, \
@@ -529,20 +590,26 @@  static const struct intel_device_info intel_skylake_gt4_info = {
 	GEN_DEFAULT_PIPEOFFSETS, \
 	IVB_CURSOR_OFFSETS, \
 	BDW_COLORS
+#endif
 
+#ifdef CONFIG_DRM_INTEL_BROXTON
 static const struct intel_device_info intel_broxton_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_BROXTON),
 	.ddb_size = 512,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEMINILAKE
 static const struct intel_device_info intel_geminilake_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_GEMINILAKE),
 	.ddb_size = 1024,
 	GLK_COLORS,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_KABYLAKE
 #define KBL_PLATFORM \
 	GEN9_FEATURES, \
 	PLATFORM(INTEL_KABYLAKE)
@@ -562,7 +629,9 @@  static const struct intel_device_info intel_kabylake_gt3_info = {
 	.gt = 3,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_COFFEELAKE
 #define CFL_PLATFORM \
 	GEN9_FEATURES, \
 	PLATFORM(INTEL_COFFEELAKE)
@@ -582,32 +651,41 @@  static const struct intel_device_info intel_coffeelake_gt3_info = {
 	.gt = 3,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN10
 #define GEN10_FEATURES \
 	GEN9_FEATURES, \
 	GEN(10), \
 	.ddb_size = 1024, \
 	.has_coherent_ggtt = false, \
 	GLK_COLORS
+#endif
 
+#ifdef CONFIG_DRM_INTEL_CANNONLAKE
 static const struct intel_device_info intel_cannonlake_info = {
 	GEN10_FEATURES,
 	PLATFORM(INTEL_CANNONLAKE),
 	.gt = 2,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN11
 #define GEN11_FEATURES \
 	GEN10_FEATURES, \
 	GEN(11), \
 	.ddb_size = 2048, \
 	.has_logical_ring_elsq = 1
+#endif
 
+#ifdef CONFIG_DRM_INTEL_ICELAKE
 static const struct intel_device_info intel_icelake_11_info = {
 	GEN11_FEATURES,
 	PLATFORM(INTEL_ICELAKE),
 	.is_alpha_support = 1,
 	.ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
 };
+#endif
 
 #undef GEN
 #undef PLATFORM
@@ -619,51 +697,102 @@  static const struct intel_device_info intel_icelake_11_info = {
  * PCI ID matches, otherwise we'll use the wrong info struct above.
  */
 static const struct pci_device_id pciidlist[] = {
+#ifdef CONFIG_DRM_INTEL_I830
 	INTEL_I830_IDS(&intel_i830_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I845
 	INTEL_I845G_IDS(&intel_i845g_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I85X
 	INTEL_I85X_IDS(&intel_i85x_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I865G
 	INTEL_I865G_IDS(&intel_i865g_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I915G
 	INTEL_I915G_IDS(&intel_i915g_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I915GM
 	INTEL_I915GM_IDS(&intel_i915gm_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I945G
 	INTEL_I945G_IDS(&intel_i945g_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I945GM
 	INTEL_I945GM_IDS(&intel_i945gm_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I965G
 	INTEL_I965G_IDS(&intel_i965g_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_G33
 	INTEL_G33_IDS(&intel_g33_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I965GM
 	INTEL_I965GM_IDS(&intel_i965gm_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_GM45
 	INTEL_GM45_IDS(&intel_gm45_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_G45
 	INTEL_G45_IDS(&intel_g45_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_PINEVIEW
 	INTEL_PINEVIEW_IDS(&intel_pineview_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_IRONLAKE
 	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
+#endif
+#ifdef CONFIG_DRM_I915_PLATFORM_INTEL_SANDYBRIDGE
 	INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
 	INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
 	INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
 	INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
+#endif
+#ifdef CONDFIG_DRM_INTEL_IVYBRIDGE
 	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 	INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
 	INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
 	INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
 	INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_HASWELL
 	INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
 	INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
 	INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_VALLEYVIEW
 	INTEL_VLV_IDS(&intel_valleyview_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_BROADWELL
 	INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 	INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 	INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_CHERRYVIEW
 	INTEL_CHV_IDS(&intel_cherryview_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_SKYLAKE
 	INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 	INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 	INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_BROXTON
 	INTEL_BXT_IDS(&intel_broxton_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_GEMINILAKE
 	INTEL_GLK_IDS(&intel_geminilake_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_KABYLAKE
 	INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 	INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 	INTEL_AML_GT2_IDS(&intel_kabylake_gt2_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_COFFEELAKE
 	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
@@ -672,8 +801,13 @@  static const struct pci_device_id pciidlist[] = {
 	INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 	INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 	INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_CANNONLAKE
 	INTEL_CNL_IDS(&intel_cannonlake_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_ICELAKE
 	INTEL_ICL_11_IDS(&intel_icelake_11_info),
+#endif
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);