[09/10] drm/i915: make GEN10 intel GPU series configurable

Submitted by Andi Shyti on Sept. 12, 2018, 1:18 p.m.

Details

Message ID 20180912131821.21339-9-andi.shyti@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX - Try Bot

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Commit Message

Andi Shyti Sept. 12, 2018, 1:18 p.m.
GEN10 consists of

  Cannon Lake

GPU.

A GEN11 define has been added because of GEN11 dependency from
GEN10 (which depends from GEN9). Without the GEN11 define, the
compile issues an error. This will be fixed in the next patch.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.sel | 16 ++++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h  |  4 ++--
 drivers/gpu/drm/i915/i915_pci.c  |  6 ++++++
 3 files changed, 22 insertions(+), 4 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/Kconfig.sel b/drivers/gpu/drm/i915/Kconfig.sel
index f495e3a29002..9b44e4becec9 100644
--- a/drivers/gpu/drm/i915/Kconfig.sel
+++ b/drivers/gpu/drm/i915/Kconfig.sel
@@ -256,9 +256,21 @@  config DRM_INTEL_COFFEELAKE
 	help
 	  Choose this option if you have a Coffee Lake gpu
 
-comment "Temporary GEN10 definition"
+comment "Intel GEN10"
 
 config DRM_INTEL_GEN10
 	bool
-	default y
 	select DRM_INTEL_GEN9
+
+config DRM_INTEL_CANNONLAKE
+	bool "Intel Cannon Lake GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN10
+	help
+	  Choose this option if you have a Cannon Lake gpu
+
+config DRM_INTEL_GEN11
+	bool
+	default y
+	select DRM_INTEL_GEN10
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d6fccc0a96f9..10485fbb4600 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2408,7 +2408,7 @@  intel_info(const struct drm_i915_private *dev_priv)
 #define IS_KABYLAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_KABYLAKE)
 #define IS_GEMINILAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 #define IS_COFFEELAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_COFFEELAKE)
-#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
+#define IS_CANNONLAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
@@ -2523,7 +2523,6 @@  intel_info(const struct drm_i915_private *dev_priv)
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
 #define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
 #define __IS_GEN_X(N, dev_priv)	__and(IS_ENABLED(CONFIG_DRIM_I915_GEN##N), \
 				!!((dev_priv)->info.gen_mask & BIT(N-1)))
@@ -2536,6 +2535,7 @@  intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN7(dev_priv)	__IS_GEN_X(7, dev_priv)
 #define IS_GEN8(dev_priv)	__IS_GEN_X(8, dev_priv)
 #define IS_GEN9(dev_priv)	__IS_GEN_X(9, dev_priv)
+#define IS_GEN10(dev_priv)	__IS_GEN_X(10, dev_priv)
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 392ed7285ef5..ce6008719869 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -653,18 +653,22 @@  static const struct intel_device_info intel_coffeelake_gt3_info = {
 };
 #endif
 
+#ifdef CONFIG_DRM_INTEL_GEN10
 #define GEN10_FEATURES \
 	GEN9_FEATURES, \
 	GEN(10), \
 	.ddb_size = 1024, \
 	.has_coherent_ggtt = false, \
 	GLK_COLORS
+#endif
 
+#ifdef CONFIG_DRM_INTEL_CANNONLAKE
 static const struct intel_device_info intel_cannonlake_info = {
 	GEN10_FEATURES,
 	PLATFORM(INTEL_CANNONLAKE),
 	.gt = 2,
 };
+#endif
 
 #define GEN11_FEATURES \
 	GEN10_FEATURES, \
@@ -794,7 +798,9 @@  static const struct pci_device_id pciidlist[] = {
 	INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 	INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 #endif
+#ifdef CONFIG_DRM_INTEL_CANNONLAKE
 	INTEL_CNL_IDS(&intel_cannonlake_info),
+#endif
 	INTEL_ICL_11_IDS(&intel_icelake_11_info),
 	{0, 0, 0}
 };