[07/10] drm/i915: make GEN8 intel GPU series configurable

Submitted by Andi Shyti on Sept. 12, 2018, 1:18 p.m.

Details

Message ID 20180912131821.21339-7-andi.shyti@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX - Try Bot

Not browsing as part of any series.

Commit Message

Andi Shyti Sept. 12, 2018, 1:18 p.m.
GEN8 consists of

  Broadwell
  Cherry view

GPUs

A GEN9 define has been added because of GEN9 dependency from
GEN8 (which depends from GEN75). Without the GEN9 define, the
compile issues an error. This will be fixed in the next patch.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.sel | 26 ++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h  |  6 +++---
 drivers/gpu/drm/i915/i915_pci.c  |  8 ++++++++
 3 files changed, 35 insertions(+), 5 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/Kconfig.sel b/drivers/gpu/drm/i915/Kconfig.sel
index ed8949010399..54a008317fea 100644
--- a/drivers/gpu/drm/i915/Kconfig.sel
+++ b/drivers/gpu/drm/i915/Kconfig.sel
@@ -188,9 +188,31 @@  config DRM_INTEL_HASWELL
 
 # this is temporary to avoid GEN8 compilation error
 
-comment "Temporary GEN8 definition"
+comment "Intel GEN8"
 
 config DRM_INTEL_GEN8
 	bool
-	default y
 	select DRM_INTEL_GEN75
+
+config DRM_INTEL_BROADWELL
+	bool "Intel Broadwell GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN8
+	help
+	  Choose this option if you have a Broadwell gpu
+
+config DRM_INTEL_CHERRYVIEW
+	bool "Intel Cherry View GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN8
+	help
+	  Choose this option if you have a Cherry View gpu
+
+comment "Temporary GEN9 definition"
+
+config DRM_INTEL_GEN9
+	bool
+	default y
+	select DRM_INTEL_GEN8
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eb3cd3d79231..037440aa4655 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2400,9 +2400,9 @@  intel_info(const struct drm_i915_private *dev_priv)
 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
 				 (dev_priv)->info.gt == 1)
 #define IS_VALLEYVIEW(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
-#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
+#define IS_CHERRYVIEW(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_HASWELL)
-#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
+#define IS_BROADWELL(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_BROADWELL)
 #define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
 #define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
 #define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
@@ -2523,7 +2523,6 @@  intel_info(const struct drm_i915_private *dev_priv)
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
 #define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
 #define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
 #define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
@@ -2536,6 +2535,7 @@  intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN5(dev_priv)	__IS_GEN_X(5, dev_priv)
 #define IS_GEN6(dev_priv)	__IS_GEN_X(6, dev_priv)
 #define IS_GEN7(dev_priv)	__IS_GEN_X(7, dev_priv)
+#define IS_GEN8(dev_priv)	__IS_GEN_X(8, dev_priv)
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4c385f04f997..97d7a4731cec 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -459,6 +459,7 @@  static const struct intel_device_info intel_haswell_gt3_info = {
 	PLATFORM(INTEL_BROADWELL)
 #endif
 
+#ifdef CONFIG_DRM_INTEL_BROADWELL
 static const struct intel_device_info intel_broadwell_gt1_info = {
 	BDW_PLATFORM,
 	.gt = 1,
@@ -482,7 +483,9 @@  static const struct intel_device_info intel_broadwell_gt3_info = {
 	.gt = 3,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_CHERRYVIEW
 static const struct intel_device_info intel_cherryview_info = {
 	PLATFORM(INTEL_CHERRYVIEW),
 	GEN(8),
@@ -506,6 +509,7 @@  static const struct intel_device_info intel_cherryview_info = {
 	CURSOR_OFFSETS,
 	CHV_COLORS,
 };
+#endif
 
 #define GEN9_DEFAULT_PAGE_SIZES \
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
@@ -738,11 +742,15 @@  static const struct pci_device_id pciidlist[] = {
 #ifdef CONFIG_DRM_INTEL_VALLEYVIEW
 	INTEL_VLV_IDS(&intel_valleyview_info),
 #endif
+#ifdef CONFIG_DRM_INTEL_BROADWELL
 	INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
 	INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
 	INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
 	INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_CHERRYVIEW
 	INTEL_CHV_IDS(&intel_cherryview_info),
+#endif
 	INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 	INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),