[08/10] drm/i915: make GEN9 intel GPU series configurable

Submitted by Andi Shyti on Sept. 12, 2018, 1:18 p.m.

Details

Message ID 20180912131821.21339-8-andi.shyti@intel.com
State New
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Series "Series without cover letter" ( rev: 1 ) in Intel GFX - Try Bot

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Commit Message

Andi Shyti Sept. 12, 2018, 1:18 p.m.
GEN9 consists of

  Sky Lake
  Broxton
  Kaby Lake
  Gemini Lake
  Coffee Lake

GPUs

A GEN10 define has been added because of GEN10 dependency from
GEN9 (which depends from GEN8). Without the GEN9 define, the
compile issues an error. This will be fixed in the next patch.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.sel | 50 ++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h  | 12 ++++----
 drivers/gpu/drm/i915/i915_pci.c  | 24 +++++++++++++++
 3 files changed, 78 insertions(+), 8 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/Kconfig.sel b/drivers/gpu/drm/i915/Kconfig.sel
index 54a008317fea..f495e3a29002 100644
--- a/drivers/gpu/drm/i915/Kconfig.sel
+++ b/drivers/gpu/drm/i915/Kconfig.sel
@@ -210,9 +210,55 @@  config DRM_INTEL_CHERRYVIEW
 	help
 	  Choose this option if you have a Cherry View gpu
 
-comment "Temporary GEN9 definition"
+comment "Intel GEN9"
 
 config DRM_INTEL_GEN9
 	bool
-	default y
 	select DRM_INTEL_GEN8
+
+config DRM_INTEL_SKYLAKE
+	bool "Intel Sky Lake GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Sky Lake gpu
+
+config DRM_INTEL_BROXTON
+	bool "Intel Broxton GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Broxton gpu
+
+config DRM_INTEL_KABYLAKE
+	bool "Intel Kaby Lake GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Kaby Lake gpu
+
+config DRM_INTEL_GEMINILAKE
+	bool "Intel Gemini Lake GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Gemini Lake gpu
+
+config DRM_INTEL_COFFEELAKE
+	bool "Intel Coffee Lake GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN9
+	help
+	  Choose this option if you have a Coffee Lake gpu
+
+comment "Temporary GEN10 definition"
+
+config DRM_INTEL_GEN10
+	bool
+	default y
+	select DRM_INTEL_GEN9
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 037440aa4655..d6fccc0a96f9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2403,11 +2403,11 @@  intel_info(const struct drm_i915_private *dev_priv)
 #define IS_CHERRYVIEW(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
 #define IS_HASWELL(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_HASWELL)
 #define IS_BROADWELL(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_BROADWELL)
-#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
-#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
-#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
-#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
-#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
+#define IS_SKYLAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_SKYLAKE)
+#define IS_BROXTON(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_BROXTON)
+#define IS_KABYLAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_KABYLAKE)
+#define IS_GEMINILAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_GEMINILAKE)
+#define IS_COFFEELAKE(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
@@ -2523,7 +2523,6 @@  intel_info(const struct drm_i915_private *dev_priv)
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
 #define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
 #define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
 #define __IS_GEN_X(N, dev_priv)	__and(IS_ENABLED(CONFIG_DRIM_I915_GEN##N), \
@@ -2536,6 +2535,7 @@  intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN6(dev_priv)	__IS_GEN_X(6, dev_priv)
 #define IS_GEN7(dev_priv)	__IS_GEN_X(7, dev_priv)
 #define IS_GEN8(dev_priv)	__IS_GEN_X(8, dev_priv)
+#define IS_GEN9(dev_priv)	__IS_GEN_X(9, dev_priv)
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97d7a4731cec..392ed7285ef5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -511,6 +511,7 @@  static const struct intel_device_info intel_cherryview_info = {
 };
 #endif
 
+#ifdef CONFIG_DRM_INTEL_GEN9
 #define GEN9_DEFAULT_PAGE_SIZES \
 	.page_sizes = I915_GTT_PAGE_SIZE_4K | \
 		      I915_GTT_PAGE_SIZE_64K | \
@@ -525,7 +526,9 @@  static const struct intel_device_info intel_cherryview_info = {
 	.has_guc = 1, \
 	.has_ipc = 1, \
 	.ddb_size = 896
+#endif
 
+#ifdef CONFIG_DRM_INTEL_SKYLAKE
 #define SKL_PLATFORM \
 	GEN9_FEATURES, \
 	PLATFORM(INTEL_SKYLAKE)
@@ -554,7 +557,9 @@  static const struct intel_device_info intel_skylake_gt4_info = {
 	SKL_GT3_PLUS_PLATFORM,
 	.gt = 4,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEN9
 #define GEN9_LP_FEATURES \
 	GEN(9), \
 	.is_lp = 1, \
@@ -585,20 +590,26 @@  static const struct intel_device_info intel_skylake_gt4_info = {
 	GEN_DEFAULT_PIPEOFFSETS, \
 	IVB_CURSOR_OFFSETS, \
 	BDW_COLORS
+#endif
 
+#ifdef CONFIG_DRM_INTEL_BROXTON
 static const struct intel_device_info intel_broxton_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_BROXTON),
 	.ddb_size = 512,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_GEMINILAKE
 static const struct intel_device_info intel_geminilake_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_GEMINILAKE),
 	.ddb_size = 1024,
 	GLK_COLORS,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_KABYLAKE
 #define KBL_PLATFORM \
 	GEN9_FEATURES, \
 	PLATFORM(INTEL_KABYLAKE)
@@ -618,7 +629,9 @@  static const struct intel_device_info intel_kabylake_gt3_info = {
 	.gt = 3,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_COFFEELAKE
 #define CFL_PLATFORM \
 	GEN9_FEATURES, \
 	PLATFORM(INTEL_COFFEELAKE)
@@ -638,6 +651,7 @@  static const struct intel_device_info intel_coffeelake_gt3_info = {
 	.gt = 3,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
+#endif
 
 #define GEN10_FEATURES \
 	GEN9_FEATURES, \
@@ -751,17 +765,26 @@  static const struct pci_device_id pciidlist[] = {
 #ifdef CONFIG_DRM_INTEL_CHERRYVIEW
 	INTEL_CHV_IDS(&intel_cherryview_info),
 #endif
+#ifdef CONFIG_DRM_INTEL_SKYLAKE
 	INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
 	INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
 	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 	INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_BROXTON
 	INTEL_BXT_IDS(&intel_broxton_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_GEMINILAKE
 	INTEL_GLK_IDS(&intel_geminilake_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_KABYLAKE
 	INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
 	INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
 	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 	INTEL_AML_GT2_IDS(&intel_kabylake_gt2_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_COFFEELAKE
 	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
 	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
 	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
@@ -770,6 +793,7 @@  static const struct pci_device_id pciidlist[] = {
 	INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
 	INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 	INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
+#endif
 	INTEL_CNL_IDS(&intel_cannonlake_info),
 	INTEL_ICL_11_IDS(&intel_icelake_11_info),
 	{0, 0, 0}