[01/10] drm/i915: make GEN2 intel GPU series configurable

Submitted by Andi Shyti on Sept. 12, 2018, 1:18 p.m.

Details

Message ID 20180912131821.21339-1-andi.shyti@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX - Try Bot

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Commit Message

Andi Shyti Sept. 12, 2018, 1:18 p.m.
GEN2 consists of:

 i830
 i845G
 i85X
 i865G

GPUs

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 drivers/gpu/drm/i915/Kconfig     |  7 ++++++-
 drivers/gpu/drm/i915/Kconfig.sel | 36 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h  | 16 +++++++++-----
 drivers/gpu/drm/i915/i915_pci.c  | 18 ++++++++++++++++
 4 files changed, 71 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/Kconfig.sel

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 33a458b7f1fc..002a63b9a701 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -28,7 +28,7 @@  config DRM_I915
 	help
 	  Choose this option if you have a system that has "Intel Graphics
 	  Media Accelerator" or "HD Graphics" integrated graphics,
-	  including 830M, 845G, 852GM, 855GM, 865G, 915G, 945G, 965G,
+	  including 915G, 945G, 965G,
 	  G35, G41, G43, G45 chipsets and Celeron, Pentium, Core i3,
 	  Core i5, Core i7 as well as Atom CPUs with integrated graphics.
 
@@ -128,6 +128,11 @@  config DRM_I915_GVT_KVMGT
 	  Choose this option if you want to enable KVMGT support for
 	  Intel GVT-g.
 
+menu "Selective selection"
+depends on DRM_I915
+source drivers/gpu/drm/i915/Kconfig.sel
+endmenu
+
 menu "drm/i915 Debugging"
 depends on DRM_I915
 depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Kconfig.sel b/drivers/gpu/drm/i915/Kconfig.sel
new file mode 100644
index 000000000000..fc1709979d21
--- /dev/null
+++ b/drivers/gpu/drm/i915/Kconfig.sel
@@ -0,0 +1,36 @@ 
+comment "Intel GEN2"
+
+config DRM_INTEL_GEN2
+	bool
+
+config DRM_INTEL_I830
+	bool "Intel i830 GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN2
+	help
+	  Choose this option if you have an i830 gpu
+
+config DRM_INTEL_I845G
+	bool "Intel i845G GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN2
+	help
+	  Choose this option if you have an i845G gpu
+
+config DRM_INTEL_I85X
+	bool "Intel i85X GPU series"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN2
+	help
+	  Choose this option if you have an i85x gpu series
+
+config DRM_INTEL_I865G
+	bool "Intel i865G GPU"
+	default y
+	depends on DRM_I915
+	select DRM_INTEL_GEN2
+	help
+	  Choose this option if you have an i865G gpu
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7ea442033a57..36356bd2efd4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2372,10 +2372,13 @@  intel_info(const struct drm_i915_private *dev_priv)
 
 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
 
-#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
-#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
-#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
-#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
+#define IS_SELECTED_PLATFORM(dev_priv, s) \
+	__and(IS_ENABLED(CONFIG_DRM_##s), IS_PLATFORM(dev_priv, s))
+
+#define IS_I830(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I830)
+#define IS_I845G(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I845G)
+#define IS_I85X(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I85X)
+#define IS_I865G(dev_priv)	IS_SELECTED_PLATFORM(dev_priv, INTEL_I865G)
 #define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
 #define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
 #define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
@@ -2517,7 +2520,6 @@  intel_info(const struct drm_i915_private *dev_priv)
  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  * chips, etc.).
  */
-#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
 #define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
 #define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
 #define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
@@ -2527,6 +2529,10 @@  intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
 #define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
 #define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
+#define __IS_GEN_X(N, dev_priv)	__and(IS_ENABLED(CONFIG_DRIM_I915_GEN##N), \
+				!!((dev_priv)->info.gen_mask & BIT(N-1)))
+
+#define IS_GEN2(dev_priv)	__IS_GEN_X(2, dev_priv)
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d6f7b9fe1d26..c2e97aac27c8 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -65,6 +65,7 @@ 
 #define GEN_DEFAULT_PAGE_SIZES \
 	.page_sizes = I915_GTT_PAGE_SIZE_4K
 
+#ifdef CONFIG_DRM_INTEL_GEN2
 #define GEN2_FEATURES \
 	GEN(2), \
 	.num_pipes = 1, \
@@ -78,19 +79,25 @@ 
 	GEN_DEFAULT_PIPEOFFSETS, \
 	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I830
 static const struct intel_device_info intel_i830_info = {
 	GEN2_FEATURES,
 	PLATFORM(INTEL_I830),
 	.is_mobile = 1, .cursor_needs_physical = 1,
 	.num_pipes = 2, /* legal, last one wins */
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I845
 static const struct intel_device_info intel_i845g_info = {
 	GEN2_FEATURES,
 	PLATFORM(INTEL_I845G),
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I85X
 static const struct intel_device_info intel_i85x_info = {
 	GEN2_FEATURES,
 	PLATFORM(INTEL_I85X),
@@ -99,11 +106,14 @@  static const struct intel_device_info intel_i85x_info = {
 	.cursor_needs_physical = 1,
 	.has_fbc = 1,
 };
+#endif
 
+#ifdef CONFIG_DRM_INTEL_I865G
 static const struct intel_device_info intel_i865g_info = {
 	GEN2_FEATURES,
 	PLATFORM(INTEL_I865G),
 };
+#endif
 
 #define GEN3_FEATURES \
 	GEN(3), \
@@ -619,10 +629,18 @@  static const struct intel_device_info intel_icelake_11_info = {
  * PCI ID matches, otherwise we'll use the wrong info struct above.
  */
 static const struct pci_device_id pciidlist[] = {
+#ifdef CONFIG_DRM_INTEL_I830
 	INTEL_I830_IDS(&intel_i830_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I845
 	INTEL_I845G_IDS(&intel_i845g_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I85X
 	INTEL_I85X_IDS(&intel_i85x_info),
+#endif
+#ifdef CONFIG_DRM_INTEL_I865G
 	INTEL_I865G_IDS(&intel_i865g_info),
+#endif
 	INTEL_I915G_IDS(&intel_i915g_info),
 	INTEL_I915GM_IDS(&intel_i915gm_info),
 	INTEL_I945G_IDS(&intel_i945g_info),