drm/i915/gvt: update force-to-nonpriv register whitelist

Submitted by Zhao, Yan Y on Sept. 12, 2018, 2:44 a.m.

Details

Message ID 20180912024429.2460-1-yan.y.zhao@intel.com
State New
Headers show
Series "drm/i915/gvt: update force-to-nonpriv register whitelist" ( rev: 1 ) in Intel GVT devel

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Commit Message

Zhao, Yan Y Sept. 12, 2018, 2:44 a.m.
register 0x83a8 should be in force-to-nonpriv whitelist as required by
windows guest

Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 1 +
 1 file changed, 1 insertion(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 290e52b1436a..bdeece7d6558 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -449,6 +449,7 @@  static i915_reg_t force_nonpriv_white_list[] = {
 	_MMIO(0x7704),
 	_MMIO(0x7708),
 	_MMIO(0x770c),
+	_MMIO(0x83a8),
 	_MMIO(0xb110),
 	GEN8_L3SQCREG4,//_MMIO(0xb118)
 	_MMIO(0xe100),

Comments

On 2018.09.11 22:44:29 -0400, Zhao Yan wrote:
> register 0x83a8 should be in force-to-nonpriv whitelist as required by
> windows guest

Anything this one fixes? What's the problem if it's not there?
Pls elaborate in your commit message.

> 
> Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/handlers.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 290e52b1436a..bdeece7d6558 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -449,6 +449,7 @@ static i915_reg_t force_nonpriv_white_list[] = {
>  	_MMIO(0x7704),
>  	_MMIO(0x7708),
>  	_MMIO(0x770c),
> +	_MMIO(0x83a8),
>  	_MMIO(0xb110),
>  	GEN8_L3SQCREG4,//_MMIO(0xb118)
>  	_MMIO(0xe100),
> -- 
> 2.17.1
> 
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