radv: adjust ESGS ring buffer size computation on VI+

Submitted by Samuel Pitoiset on Sept. 10, 2018, 4:03 p.m.

Details

Message ID 20180910160312.19901-1-samuel.pitoiset@gmail.com
State New
Headers show
Series "radv: adjust ESGS ring buffer size computation on VI+" ( rev: 1 ) in Mesa

Not browsing as part of any series.

Commit Message

Samuel Pitoiset Sept. 10, 2018, 4:03 p.m.
Noticed while working in this area. Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
---
 src/amd/vulkan/radv_pipeline.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Patch hide | download patch | download mbox

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1741d5e9047..e362c380453 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1575,7 +1575,11 @@  calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta
 	unsigned num_se = device->physical_device->rad_info.max_se;
 	unsigned wave_size = 64;
 	unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
-	unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
+	/* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
+	 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
+	 */
+	unsigned gs_vertex_reuse =
+		device->physical_device->rad_info.chip_class >= VI ? 32 : 16;
 	unsigned alignment = 256 * num_se;
 	/* The maximum size is 63.999 MB per SE. */
 	unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;

Comments

On Mon, Sep 10, 2018 at 12:03 PM, Samuel Pitoiset
<samuel.pitoiset@gmail.com> wrote:
> Noticed while working in this area. Ported from RadeonSI.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
> ---
>  src/amd/vulkan/radv_pipeline.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 1741d5e9047..e362c380453 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -1575,7 +1575,11 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta
>         unsigned num_se = device->physical_device->rad_info.max_se;
>         unsigned wave_size = 64;
>         unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
> -       unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
> +       /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
> +        * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
> +        */
> +       unsigned gs_vertex_reuse =
> +               device->physical_device->rad_info.chip_class >= VI ? 32 : 16;

I have no idea what any of these things are, but just would like to
observe that previously it was scaled by num_se, while now it is no
longer.

  -ilia
On 9/10/18 6:12 PM, Ilia Mirkin wrote:
> On Mon, Sep 10, 2018 at 12:03 PM, Samuel Pitoiset
> <samuel.pitoiset@gmail.com> wrote:
>> Noticed while working in this area. Ported from RadeonSI.
>>
>> Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
>> ---
>>   src/amd/vulkan/radv_pipeline.c | 6 +++++-
>>   1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
>> index 1741d5e9047..e362c380453 100644
>> --- a/src/amd/vulkan/radv_pipeline.c
>> +++ b/src/amd/vulkan/radv_pipeline.c
>> @@ -1575,7 +1575,11 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta
>>          unsigned num_se = device->physical_device->rad_info.max_se;
>>          unsigned wave_size = 64;
>>          unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
>> -       unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
>> +       /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
>> +        * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
>> +        */
>> +       unsigned gs_vertex_reuse =
>> +               device->physical_device->rad_info.chip_class >= VI ? 32 : 16;
> 
> I have no idea what any of these things are, but just would like to
> observe that previously it was scaled by num_se, while now it is no
> longer.

'* num_se' decided to disappear, thanks for catching this :)

> 
>    -ilia
>