[v1] drm/i915: Skip modeset for cdclk changes if possible

Submitted by Kumar, Abhay on Aug. 27, 2018, 6:50 p.m.

Details

Message ID 1535395832-32264-1-git-send-email-abhay.kumar@intel.com
State New
Headers show
Series "drm/i915: Skip modeset for cdclk changes if possible" ( rev: 1 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Kumar, Abhay Aug. 27, 2018, 6:50 p.m.
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |   3 +-
 drivers/gpu/drm/i915/i915_reg.h      |   3 +-
 drivers/gpu/drm/i915/intel_cdclk.c   | 105 +++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_display.c |  20 ++++++-
 drivers/gpu/drm/i915/intel_drv.h     |   9 ++-
 5 files changed, 105 insertions(+), 35 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e5b9d3c77139..1f0a6427e76c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -408,7 +408,8 @@  struct drm_i915_display_funcs {
 	void (*get_cdclk)(struct drm_i915_private *dev_priv,
 			  struct intel_cdclk_state *cdclk_state);
 	void (*set_cdclk)(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_state *cdclk_state);
+			  const struct intel_cdclk_state *cdclk_state,
+			  enum pipe pipe);
 	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
 			     enum i9xx_plane_id i9xx_plane);
 	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88a60f6..7702cec70b0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9262,7 +9262,8 @@  enum skl_power_gate {
 #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
 #define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
 #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
-#define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
+#define  ICL_CDCLK_CD2X_PIPE(pipe)	((pipe) << 19)
+#define  ICL_CDCLK_CD2X_PIPE_NONE	ICL_CDCLK_CD2X_PIPE(7)
 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)
 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
 
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 29075c763428..1955f6aa54e1 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -516,7 +516,8 @@  static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 }
 
 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_state *cdclk_state)
+			  const struct intel_cdclk_state *cdclk_state,
+			  enum pipe pipe)
 {
 	int cdclk = cdclk_state->cdclk;
 	u32 val, cmd = cdclk_state->voltage_level;
@@ -597,7 +598,8 @@  static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 }
 
 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_state *cdclk_state)
+			  const struct intel_cdclk_state *cdclk_state,
+			  enum pipe pipe)
 {
 	int cdclk = cdclk_state->cdclk;
 	u32 val, cmd = cdclk_state->voltage_level;
@@ -695,7 +697,8 @@  static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 }
 
 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_state *cdclk_state)
+			  const struct intel_cdclk_state *cdclk_state,
+			  enum pipe pipe)
 {
 	int cdclk = cdclk_state->cdclk;
 	uint32_t val;
@@ -985,7 +988,8 @@  static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 }
 
 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_state *cdclk_state)
+			  const struct intel_cdclk_state *cdclk_state,
+			  enum pipe pipe)
 {
 	int cdclk = cdclk_state->cdclk;
 	int vco = cdclk_state->vco;
@@ -1156,7 +1160,7 @@  void skl_init_cdclk(struct drm_i915_private *dev_priv)
 	cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
 	cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
 
-	skl_set_cdclk(dev_priv, &cdclk_state);
+	skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 /**
@@ -1174,7 +1178,7 @@  void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 	cdclk_state.vco = 0;
 	cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
 
-	skl_set_cdclk(dev_priv, &cdclk_state);
+	skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 static int bxt_calc_cdclk(int min_cdclk)
@@ -1353,7 +1357,8 @@  static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
 }
 
 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_state *cdclk_state)
+			  const struct intel_cdclk_state *cdclk_state,
+			  enum pipe pipe)
 {
 	int cdclk = cdclk_state->cdclk;
 	int vco = cdclk_state->vco;
@@ -1406,11 +1411,10 @@  static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 		bxt_de_pll_enable(dev_priv, vco);
 
 	val = divider | skl_cdclk_decimal(cdclk);
-	/*
-	 * FIXME if only the cd2x divider needs changing, it could be done
-	 * without shutting off the pipe (if only one pipe is active).
-	 */
-	val |= BXT_CDCLK_CD2X_PIPE_NONE;
+	if (pipe == INVALID_PIPE)
+		val |= BXT_CDCLK_CD2X_PIPE_NONE;
+	else
+		val |= BXT_CDCLK_CD2X_PIPE(pipe);
 	/*
 	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
 	 * enable otherwise.
@@ -1523,7 +1527,7 @@  void bxt_init_cdclk(struct drm_i915_private *dev_priv)
 	}
 	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
 
-	bxt_set_cdclk(dev_priv, &cdclk_state);
+	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 /**
@@ -1541,7 +1545,7 @@  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
 	cdclk_state.vco = 0;
 	cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
 
-	bxt_set_cdclk(dev_priv, &cdclk_state);
+	bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 static int cnl_calc_cdclk(int min_cdclk)
@@ -1661,7 +1665,8 @@  static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
 }
 
 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_state *cdclk_state)
+			  const struct intel_cdclk_state *cdclk_state,
+			  enum pipe pipe)
 {
 	int cdclk = cdclk_state->cdclk;
 	int vco = cdclk_state->vco;
@@ -1702,11 +1707,10 @@  static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 		cnl_cdclk_pll_enable(dev_priv, vco);
 
 	val = divider | skl_cdclk_decimal(cdclk);
-	/*
-	 * FIXME if only the cd2x divider needs changing, it could be done
-	 * without shutting off the pipe (if only one pipe is active).
-	 */
-	val |= BXT_CDCLK_CD2X_PIPE_NONE;
+	if (pipe == INVALID_PIPE)
+		val |= BXT_CDCLK_CD2X_PIPE_NONE;
+	else
+		val |= BXT_CDCLK_CD2X_PIPE(pipe);
 	I915_WRITE(CDCLK_CTL, val);
 
 	/* inform PCU of the change */
@@ -1845,10 +1849,12 @@  static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
 }
 
 static void icl_set_cdclk(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_state *cdclk_state)
+			  const struct intel_cdclk_state *cdclk_state,
+			  enum pipe pipe)
 {
 	unsigned int cdclk = cdclk_state->cdclk;
 	unsigned int vco = cdclk_state->vco;
+	u32 val;
 	int ret;
 
 	mutex_lock(&dev_priv->pcu_lock);
@@ -1870,8 +1876,12 @@  static void icl_set_cdclk(struct drm_i915_private *dev_priv,
 	if (dev_priv->cdclk.hw.vco != vco)
 		cnl_cdclk_pll_enable(dev_priv, vco);
 
-	I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
-			      skl_cdclk_decimal(cdclk));
+	val = skl_cdclk_decimal(cdclk);
+	if (pipe == INVALID_PIPE)
+		val |= ICL_CDCLK_CD2X_PIPE_NONE;
+	else
+		val |= ICL_CDCLK_CD2X_PIPE(pipe);
+	I915_WRITE(CDCLK_CTL, val);
 
 	mutex_lock(&dev_priv->pcu_lock);
 	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
@@ -2000,7 +2010,7 @@  void icl_init_cdclk(struct drm_i915_private *dev_priv)
 	sanitized_state.voltage_level =
 				icl_calc_voltage_level(sanitized_state.cdclk);
 
-	icl_set_cdclk(dev_priv, &sanitized_state);
+	icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
 }
 
 /**
@@ -2018,7 +2028,7 @@  void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
 	cdclk_state.vco = 0;
 	cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
 
-	icl_set_cdclk(dev_priv, &cdclk_state);
+	icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 /**
@@ -2046,7 +2056,7 @@  void cnl_init_cdclk(struct drm_i915_private *dev_priv)
 	cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
 	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
 
-	cnl_set_cdclk(dev_priv, &cdclk_state);
+	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 /**
@@ -2064,7 +2074,7 @@  void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
 	cdclk_state.vco = 0;
 	cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
 
-	cnl_set_cdclk(dev_priv, &cdclk_state);
+	cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
 }
 
 /**
@@ -2084,6 +2094,41 @@  bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
 }
 
 /**
+ * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update
+ * @a: first CDCLK state
+ * @b: second CDCLK state
+ *
+ * Returns:
+ * True if the CDCLK states require just a cd2x divider update, false if not.
+ */
+bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
+				   const struct intel_cdclk_state *a,
+				   const struct intel_cdclk_state *b)
+{
+	/* Older hw doesn't have the capability */
+	if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
+		return false;
+
+	return a->cdclk != b->cdclk &&
+		a->vco == b->vco &&
+		a->ref == b->ref;
+}
+
+/**
+ * intel_cdclk_can_skip_modeset - Determine if two CDCLK states can a modeset on all pipes
+ * @a: first CDCLK state
+ * @b: second CDCLK state
+ *
+ * Returns:
+ * True if the CDCLK states require pipes to be off during reprogramming, false if not.
+ */
+bool intel_cdclk_can_skip_modeset(const struct intel_cdclk_state *a,
+				  const struct intel_cdclk_state *b)
+{
+	return a->vco == b->vco && a->ref == b->ref;
+}
+
+/**
  * intel_cdclk_changed - Determine if two CDCLK states are different
  * @a: first CDCLK state
  * @b: second CDCLK state
@@ -2111,12 +2156,14 @@  void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
  * intel_set_cdclk - Push the CDCLK state to the hardware
  * @dev_priv: i915 device
  * @cdclk_state: new CDCLK state
+ * @pipe: pipe with which to synchronize the update
  *
  * Program the hardware based on the passed in CDCLK state,
  * if necessary.
  */
 void intel_set_cdclk(struct drm_i915_private *dev_priv,
-		     const struct intel_cdclk_state *cdclk_state)
+		     const struct intel_cdclk_state *cdclk_state,
+		     enum pipe pipe)
 {
 	if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
 		return;
@@ -2126,7 +2173,7 @@  void intel_set_cdclk(struct drm_i915_private *dev_priv,
 
 	intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
 
-	dev_priv->display.set_cdclk(dev_priv, cdclk_state);
+	dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe);
 
 	if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
 		 "cdclk state doesn't match!\n")) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b0b6e1e9a294..5a67fb39300a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12217,6 +12217,7 @@  static int intel_modeset_checks(struct drm_atomic_state *state)
 	intel_state->active_crtcs = dev_priv->active_crtcs;
 	intel_state->cdclk.logical = dev_priv->cdclk.logical;
 	intel_state->cdclk.actual = dev_priv->cdclk.actual;
+	intel_state->cdclk.pipe = INVALID_PIPE;
 
 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 		if (new_crtc_state->active)
@@ -12252,12 +12253,24 @@  static int intel_modeset_checks(struct drm_atomic_state *state)
 				return ret;
 		}
 
+
 		/* All pipes must be switched off while we change the cdclk. */
-		if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
-					      &intel_state->cdclk.actual)) {
+		if (is_power_of_2(intel_state->active_crtcs) &&
+		    intel_cdclk_needs_cd2x_update(dev_priv,
+						  &dev_priv->cdclk.actual,
+						  &intel_state->cdclk.actual)) {
+			ret = intel_lock_all_pipes(state);
+			if (ret < 0)
+				return ret;
+
+			intel_state->cdclk.pipe = ilog2(intel_state->active_crtcs);
+		} else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
+						     &intel_state->cdclk.actual)) {
 			ret = intel_modeset_all_pipes(state);
 			if (ret < 0)
 				return ret;
+
+			intel_state->cdclk.pipe = INVALID_PIPE;
 		}
 
 		DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
@@ -12650,7 +12663,8 @@  static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 	if (intel_state->modeset) {
 		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
 
-		intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
+		intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual,
+				intel_state->cdclk.pipe);
 
 		/*
 		 * SKL workaround: bspec recommends we disable the SAGV when we
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 843eefaa0f0c..e5ffe42084a5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -456,6 +456,9 @@  struct intel_atomic_state {
 		 * state only when all crtc's are DPMS off.
 		 */
 		struct intel_cdclk_state actual;
+
+		/* pipe to which cd2x update is synchronized */
+		enum pipe pipe;
 	} cdclk;
 
 	bool dpll_set, modeset;
@@ -1464,12 +1467,16 @@  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
 void intel_update_cdclk(struct drm_i915_private *dev_priv);
 void intel_update_rawclk(struct drm_i915_private *dev_priv);
+bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
+				   const struct intel_cdclk_state *a,
+				   const struct intel_cdclk_state *b);
 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
 			       const struct intel_cdclk_state *b);
 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
 			 const struct intel_cdclk_state *b);
 void intel_set_cdclk(struct drm_i915_private *dev_priv,
-		     const struct intel_cdclk_state *cdclk_state);
+		     const struct intel_cdclk_state *cdclk_state,
+		     enum pipe pipe);
 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
 			    const char *context);
 

Comments

On Mon, Aug 27, 2018 at 11:50:32AM -0700, Abhay Kumar wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> If we have only a single active pipe and the cdclk change only requires
> the cd2x divider to be updated bxt+ can do the update with forcing a full
> modeset on the pipe. Try to hook that up.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |   3 +-
>  drivers/gpu/drm/i915/i915_reg.h      |   3 +-
>  drivers/gpu/drm/i915/intel_cdclk.c   | 105 +++++++++++++++++++++++++----------
>  drivers/gpu/drm/i915/intel_display.c |  20 ++++++-
>  drivers/gpu/drm/i915/intel_drv.h     |   9 ++-
>  5 files changed, 105 insertions(+), 35 deletions(-)
> 
<snip>
> @@ -12252,12 +12253,24 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>  				return ret;
>  		}
>  
> +
>  		/* All pipes must be switched off while we change the cdclk. */
> -		if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
> -					      &intel_state->cdclk.actual)) {
> +		if (is_power_of_2(intel_state->active_crtcs) &&
> +		    intel_cdclk_needs_cd2x_update(dev_priv,
> +						  &dev_priv->cdclk.actual,
> +						  &intel_state->cdclk.actual)) {
> +			ret = intel_lock_all_pipes(state);
> +			if (ret < 0)
> +				return ret;
> +
> +			intel_state->cdclk.pipe = ilog2(intel_state->active_crtcs);

BTW on further reflection this probably isn't quite sufficient. Let's
say we have a commit with allow_modeset=true, but we aren't actually
required to do a modeset based on any of the state changes. If we still
have to change cdclk we should actually be doing the cd2x update
atomically with the plane updates, or we should do it before or after
the plane updates depending on whether the cdclk freq is going up or
down.

Doing the update atomically with the plane updates might be nicer in the
end, but for that we would likely need to split the .set_cdclk() hooks
into three parts (pre+commit+post). Whereas just doing the update before
or after the plane updates as needed would probably be a little simpler.


> +		} else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
> +						     &intel_state->cdclk.actual)) {
>  			ret = intel_modeset_all_pipes(state);
>  			if (ret < 0)
>  				return ret;
> +
> +			intel_state->cdclk.pipe = INVALID_PIPE;
>  		}
>  
>  		DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
On 8/28/2018 5:39 AM, Ville Syrjälä wrote:
> On Mon, Aug 27, 2018 at 11:50:32AM -0700, Abhay Kumar wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> If we have only a single active pipe and the cdclk change only requires
>> the cd2x divider to be updated bxt+ can do the update with forcing a full
>> modeset on the pipe. Try to hook that up.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h      |   3 +-
>>   drivers/gpu/drm/i915/i915_reg.h      |   3 +-
>>   drivers/gpu/drm/i915/intel_cdclk.c   | 105 +++++++++++++++++++++++++----------
>>   drivers/gpu/drm/i915/intel_display.c |  20 ++++++-
>>   drivers/gpu/drm/i915/intel_drv.h     |   9 ++-
>>   5 files changed, 105 insertions(+), 35 deletions(-)
>>
> <snip>
>> @@ -12252,12 +12253,24 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>>   				return ret;
>>   		}
>>   
>> +
>>   		/* All pipes must be switched off while we change the cdclk. */
>> -		if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
>> -					      &intel_state->cdclk.actual)) {
>> +		if (is_power_of_2(intel_state->active_crtcs) &&
>> +		    intel_cdclk_needs_cd2x_update(dev_priv,
>> +						  &dev_priv->cdclk.actual,
>> +						  &intel_state->cdclk.actual)) {
>> +			ret = intel_lock_all_pipes(state);
>> +			if (ret < 0)
>> +				return ret;
>> +
>> +			intel_state->cdclk.pipe = ilog2(intel_state->active_crtcs);
> BTW on further reflection this probably isn't quite sufficient. Let's
> say we have a commit with allow_modeset=true, but we aren't actually
> required to do a modeset based on any of the state changes. If we still
> have to change cdclk we should actually be doing the cd2x update
> atomically with the plane updates, or we should do it before or after
> the plane updates depending on whether the cdclk freq is going up or
> down.
>
> Doing the update atomically with the plane updates might be nicer in the
> end, but for that we would likely need to split the .set_cdclk() hooks
> into three parts (pre+commit+post). Whereas just doing the update before
> or after the plane updates as needed would probably be a little simpler.
Yeah. That might also get rid of cdclk mismatch warning during multiple 
suspend resume cycle.

[280.600259] cdclk state doesn't match!

[280.600270] calling1-8+ @ 3110, parent: usb1, cb: usb_dev_resume

[280.600276] WARNING: CPU: 3 PID: 5224 at 
/mnt/host/source/src/third_party/ker

nel/v4.14/drivers/gpu/drm/i915/intel_cdclk.c:1867 intel_set_cdclk+0xaa/0xdb

[280.600277] Modules linked in: cmac rfcomm uinput 
snd_soc_sst_bxt_da7219_max9

8357a snd_soc_hdac_hdmi snd_soc_dmic lzo lzo_compress snd_soc_skl 
snd_soc_skl_ip

c snd_soc_sst_ipc snd_soc_sst_dsp snd_soc_acpi snd_hda_ext_core snd_hda_core

[280.600307] callingphy0+ @ 3102, parent: 0000:00:0c.0, cb: wiphy_resume [cf

g80211]

[280.600308]zram snd_soc_max98357a acpi_als snd_soc_da7219 bridge stp llc ip

t_MASQUERADE nf_nat_masquerade_ipv4 xt_mark fuse snd_seq_dummy snd_seq 
snd_seq_d

evice btusb btrtl btbcm iio_trig_sysfs btintel uvcvideo bluetooth 
videobuf2_vmal

loc videobuf2_memops videobuf2_v4l2 ecdh_generic videobuf2_core 
cros_ec_sensors

cros_ec_sensors_ring cros_ec_sensors_core industrialio_triggered_buffer 
kfifo_bu

[280.600346] RDX: ffffffffb8258dd0 RSI: 0000000000000002 RDI: 
ffffffffb8258db0

[280.600347] RBP: ffffbb9546b73aa0 R08: 0000000000000000 R09: 
0000000000000000

[280.600348] R10: 0000000000000000 R11: ffffffffb86d8518 R12: 
ffffa22075790000

[280.600349] R13: ffffa22075793d24 R14: 00000000ffffffff R15: 
ffffa2202eec9800

00000000000

[280.600352] CS:0010 DS: 0000 ES: 0000 CR0: 0000000080050033

[280.600353] CR2: 00007f43c04d0e50 CR3: 0000000224112000 CR4: 
00000000003406e0

[280.600354] Call Trace:

[280.600361]intel_atomic_commit_tail+0x20a/0xacb

[280.600363]? intel_atomic_commit_ready+0x44/0x4c

[280.600365]intel_atomic_commit+0x227/0x238

[280.600368]glk_force_audio_cdclk+0x9f/0x119

[280.600370]i915_audio_component_get_power+0x3e/0x4d

[280.600376]snd_hdac_display_power+0x53/0x97 [snd_hda_core]

[280.600379] calling1-9+ @ 3086, parent: usb1, cb: usb_dev_resume

[280.600384]skl_resume+0x3a/0x17a [snd_soc_skl]

[280.600387]? pci_pm_suspend_noirq+0x1e9/0x1e9

[280.600391]dpm_run_callback+0x59/0xbf

[280.600394]device_resume+0x192/0x1d4

[280.600396]dpm_resume+0x145/0x1da

[280.600398]dpm_resume_end+0x11/0x1a

[280.600403]suspend_devices_and_enter+0x354/0x5c2

[280.600407]? remove_wait_queue+0x51/0x51

[280.600409]pm_suspend+0x29c/0x2e2

[280.600411]state_store+0xa2/0xcb

[280.600415]kernfs_fop_write+0x103/0x14a

[280.600420]__vfs_write+0x37/0xd0

[280.600424]? inode_security+0x19/0x20

[280.600426]? selinux_file_permission+0x78/0xad

[280.600428]vfs_write+0xb9/0xfd

[280.600430]SyS_write+0x5f/0xa3

[280.600434]do_syscall_64+0x64/0x72

[280.600438]entry_SYSCALL_64_after_hwframe+0x3d/0xa2

[280.600441] RIP: 0033:0x7f969d8af3b0

00001

[280.600443] RAX: ffffffffffffffda RBX: 00007f969ddf0000 RCX: 
00007f969d8af3b0

[280.600444] RDX: 0000000000000006 RSI: 00007f969ddf0000 RDI: 
0000000000000001

[280.600445] RBP: 00007ffd9e3f4880 R08: ffffffffffffffff R09: 
0000000000000000

[280.600446] R10: 0000000000001000 R11: 0000000000000246 R12: 
0000000000000006

[280.600447] R13: 0000000000020000 R14: 00007f969ddf0000 R15: 
0000000000000001


>
>
>> +		} else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
>> +						     &intel_state->cdclk.actual)) {
>>   			ret = intel_modeset_all_pipes(state);
>>   			if (ret < 0)
>>   				return ret;
>> +
>> +			intel_state->cdclk.pipe = INVALID_PIPE;
>>   		}
>>   
>>   		DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
+Susanta

From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Kumar, Abhay
Sent: Tuesday, August 28, 2018 5:55 PM
To: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v1] drm/i915: Skip modeset for cdclk changes if possible




On 8/28/2018 5:39 AM, Ville Syrjälä wrote:

On Mon, Aug 27, 2018 at 11:50:32AM -0700, Abhay Kumar wrote:

From: Ville Syrjälä <ville.syrjala@linux.intel.com><mailto:ville.syrjala@linux.intel.com>



If we have only a single active pipe and the cdclk change only requires

the cd2x divider to be updated bxt+ can do the update with forcing a full

modeset on the pipe. Try to hook that up.



Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com><mailto:ville.syrjala@linux.intel.com>

Signed-off-by: Abhay Kumar <abhay.kumar@intel.com><mailto:abhay.kumar@intel.com>

---

 drivers/gpu/drm/i915/i915_drv.h      |   3 +-

 drivers/gpu/drm/i915/i915_reg.h      |   3 +-

 drivers/gpu/drm/i915/intel_cdclk.c   | 105 +++++++++++++++++++++++++----------

 drivers/gpu/drm/i915/intel_display.c |  20 ++++++-

 drivers/gpu/drm/i915/intel_drv.h     |   9 ++-

 5 files changed, 105 insertions(+), 35 deletions(-)



<snip>

@@ -12252,12 +12253,24 @@ static int intel_modeset_checks(struct drm_atomic_state *state)

                          return ret;

           }



+

           /* All pipes must be switched off while we change the cdclk. */

-          if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,

-                                       &intel_state->cdclk.actual)) {

+          if (is_power_of_2(intel_state->active_crtcs) &&

+              intel_cdclk_needs_cd2x_update(dev_priv,

+                                          &dev_priv->cdclk.actual,

+                                          &intel_state->cdclk.actual)) {

+                  ret = intel_lock_all_pipes(state);

+                  if (ret < 0)

+                         return ret;

+

+                  intel_state->cdclk.pipe = ilog2(intel_state->active_crtcs);



BTW on further reflection this probably isn't quite sufficient. Let's

say we have a commit with allow_modeset=true, but we aren't actually

required to do a modeset based on any of the state changes. If we still

have to change cdclk we should actually be doing the cd2x update

atomically with the plane updates, or we should do it before or after

the plane updates depending on whether the cdclk freq is going up or

down.



Doing the update atomically with the plane updates might be nicer in the

end, but for that we would likely need to split the .set_cdclk() hooks

into three parts (pre+commit+post). Whereas just doing the update before

or after the plane updates as needed would probably be a little simpler.
Yeah. That might also get rid of cdclk mismatch warning during multiple suspend resume cycle.

[  280.600259] cdclk state doesn't match!

[  280.600270] calling  1-8+ @ 3110, parent: usb1, cb: usb_dev_resume

[  280.600276] WARNING: CPU: 3 PID: 5224 at /mnt/host/source/src/third_party/ker

nel/v4.14/drivers/gpu/drm/i915/intel_cdclk.c:1867 intel_set_cdclk+0xaa/0xdb

[  280.600277] Modules linked in: cmac rfcomm uinput snd_soc_sst_bxt_da7219_max9

8357a snd_soc_hdac_hdmi snd_soc_dmic lzo lzo_compress snd_soc_skl snd_soc_skl_ip

c snd_soc_sst_ipc snd_soc_sst_dsp snd_soc_acpi snd_hda_ext_core snd_hda_core

[  280.600307] calling  phy0+ @ 3102, parent: 0000:00:0c.0, cb: wiphy_resume [cf

g80211]

[  280.600308]  zram snd_soc_max98357a acpi_als snd_soc_da7219 bridge stp llc ip

t_MASQUERADE nf_nat_masquerade_ipv4 xt_mark fuse snd_seq_dummy snd_seq snd_seq_d

evice btusb btrtl btbcm iio_trig_sysfs btintel uvcvideo bluetooth videobuf2_vmal

loc videobuf2_memops videobuf2_v4l2 ecdh_generic videobuf2_core cros_ec_sensors

cros_ec_sensors_ring cros_ec_sensors_core industrialio_triggered_buffer kfifo_bu

[  280.600346] RDX: ffffffffb8258dd0 RSI: 0000000000000002 RDI: ffffffffb8258db0

[  280.600347] RBP: ffffbb9546b73aa0 R08: 0000000000000000 R09: 0000000000000000

[  280.600348] R10: 0000000000000000 R11: ffffffffb86d8518 R12: ffffa22075790000

[  280.600349] R13: ffffa22075793d24 R14: 00000000ffffffff R15: ffffa2202eec9800

00000000000

[  280.600352] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033

[  280.600353] CR2: 00007f43c04d0e50 CR3: 0000000224112000 CR4: 00000000003406e0

[  280.600354] Call Trace:

[  280.600361]  intel_atomic_commit_tail+0x20a/0xacb

[  280.600363]  ? intel_atomic_commit_ready+0x44/0x4c

[  280.600365]  intel_atomic_commit+0x227/0x238

[  280.600368]  glk_force_audio_cdclk+0x9f/0x119

[  280.600370]  i915_audio_component_get_power+0x3e/0x4d

[  280.600376]  snd_hdac_display_power+0x53/0x97 [snd_hda_core]

[  280.600379] calling  1-9+ @ 3086, parent: usb1, cb: usb_dev_resume

[  280.600384]  skl_resume+0x3a/0x17a [snd_soc_skl]

[  280.600387]  ? pci_pm_suspend_noirq+0x1e9/0x1e9

[  280.600391]  dpm_run_callback+0x59/0xbf

[  280.600394]  device_resume+0x192/0x1d4

[  280.600396]  dpm_resume+0x145/0x1da

[  280.600398]  dpm_resume_end+0x11/0x1a

[  280.600403]  suspend_devices_and_enter+0x354/0x5c2

[  280.600407]  ? remove_wait_queue+0x51/0x51

[  280.600409]  pm_suspend+0x29c/0x2e2

[  280.600411]  state_store+0xa2/0xcb

[  280.600415]  kernfs_fop_write+0x103/0x14a

[  280.600420]  __vfs_write+0x37/0xd0

[  280.600424]  ? inode_security+0x19/0x20

[  280.600426]  ? selinux_file_permission+0x78/0xad

[  280.600428]  vfs_write+0xb9/0xfd

[  280.600430]  SyS_write+0x5f/0xa3

[  280.600434]  do_syscall_64+0x64/0x72

[  280.600438]  entry_SYSCALL_64_after_hwframe+0x3d/0xa2

[  280.600441] RIP: 0033:0x7f969d8af3b0

00001

[  280.600443] RAX: ffffffffffffffda RBX: 00007f969ddf0000 RCX: 00007f969d8af3b0

[  280.600444] RDX: 0000000000000006 RSI: 00007f969ddf0000 RDI: 0000000000000001

[  280.600445] RBP: 00007ffd9e3f4880 R08: ffffffffffffffff R09: 0000000000000000

[  280.600446] R10: 0000000000001000 R11: 0000000000000246 R12: 0000000000000006

[  280.600447] R13: 0000000000020000 R14: 00007f969ddf0000 R15: 0000000000000001









+          } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,

+                                             &intel_state->cdclk.actual)) {

                   ret = intel_modeset_all_pipes(state);

                   if (ret < 0)

                          return ret;

+

+                  intel_state->cdclk.pipe = INVALID_PIPE;

           }



           DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",