[12/13] winsys/amdgpu: add vcn jpeg cs support

Submitted by Zhang, Boyuan on Aug. 16, 2018, 4:06 p.m.

Details

Message ID 1534435591-22542-12-git-send-email-boyuan.zhang@amd.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Mesa

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Commit Message

Zhang, Boyuan Aug. 16, 2018, 4:06 p.m.
From: Boyuan Zhang <boyuan.zhang@amd.com>

Add vcn jpeg cs support, align cs by no-op.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Patch hide | download patch | download mbox

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a3feeb9..5092f49 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -840,6 +840,10 @@  static bool amdgpu_init_cs_context(struct amdgpu_cs_context *cs,
       cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
       break;
 
+   case RING_VCN_JPEG:
+      cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
+      break;
+
    default:
    case RING_GFX:
       cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_GFX;
@@ -1545,6 +1549,14 @@  static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
       while (rcs->current.cdw & 15)
          radeon_emit(rcs, 0x80000000); /* type2 nop packet */
       break;
+   case RING_VCN_JPEG:
+      if (rcs->current.cdw % 2)
+         assert(0);
+      while (rcs->current.cdw & 15) {
+         radeon_emit(rcs, 0x60000000); /* nop packet */
+         radeon_emit(rcs, 0x00000000);
+      }
+      break;
    case RING_VCN_DEC:
       while (rcs->current.cdw & 15)
          radeon_emit(rcs, 0x81ff); /* nop packet */

Comments

On 08/16/2018 12:06 PM, boyuan.zhang@amd.com wrote:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Add vcn jpeg cs support, align cs by no-op.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> ---
>   src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> index a3feeb9..5092f49 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> @@ -840,6 +840,10 @@ static bool amdgpu_init_cs_context(struct amdgpu_cs_context *cs,
>         cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
>         break;
>   
> +   case RING_VCN_JPEG:
> +      cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
> +      break;
> +
>      default:
>      case RING_GFX:
>         cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_GFX;
> @@ -1545,6 +1549,14 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
>         while (rcs->current.cdw & 15)
>            radeon_emit(rcs, 0x80000000); /* type2 nop packet */
>         break;
> +   case RING_VCN_JPEG:
> +      if (rcs->current.cdw % 2)
> +         assert(0);
> +      while (rcs->current.cdw & 15) {
> +         radeon_emit(rcs, 0x60000000); /* nop packet */
> +         radeon_emit(rcs, 0x00000000);
> +      }
> +      break;
>      case RING_VCN_DEC:
>         while (rcs->current.cdw & 15)
>            radeon_emit(rcs, 0x81ff); /* nop packet */
The patch is:
Reviewed-by: Leo Liu <leo.liu@amd.com>

BTW, if you got chance, please fix the NOP for VCN DEC here in the same 
way. i.e 0x81ff and 0.

Regards,
Leo
On 2018-08-16 01:41 PM, Leo Liu wrote:
>
>
> On 08/16/2018 12:06 PM, boyuan.zhang@amd.com wrote:
>> From: Boyuan Zhang <boyuan.zhang@amd.com>
>>
>> Add vcn jpeg cs support, align cs by no-op.
>>
>> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
>> ---
>>   src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
>> b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
>> index a3feeb9..5092f49 100644
>> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
>> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
>> @@ -840,6 +840,10 @@ static bool amdgpu_init_cs_context(struct 
>> amdgpu_cs_context *cs,
>>         cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
>>         break;
>>   +   case RING_VCN_JPEG:
>> +      cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
>> +      break;
>> +
>>      default:
>>      case RING_GFX:
>>         cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_GFX;
>> @@ -1545,6 +1549,14 @@ static int amdgpu_cs_flush(struct 
>> radeon_winsys_cs *rcs,
>>         while (rcs->current.cdw & 15)
>>            radeon_emit(rcs, 0x80000000); /* type2 nop packet */
>>         break;
>> +   case RING_VCN_JPEG:
>> +      if (rcs->current.cdw % 2)
>> +         assert(0);
>> +      while (rcs->current.cdw & 15) {
>> +         radeon_emit(rcs, 0x60000000); /* nop packet */
>> +         radeon_emit(rcs, 0x00000000);
>> +      }
>> +      break;
>>      case RING_VCN_DEC:
>>         while (rcs->current.cdw & 15)
>>            radeon_emit(rcs, 0x81ff); /* nop packet */
> The patch is:
> Reviewed-by: Leo Liu <leo.liu@amd.com>
>
> BTW, if you got chance, please fix the NOP for VCN DEC here in the 
> same way. i.e 0x81ff and 0.
>
> Regards,
> Leo
>

Sure, I will prepare a separate patch for that.

Regards,
Boyuan

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