[11/13] amd/common: add vcn jpeg ip info query

Submitted by Zhang, Boyuan on Aug. 16, 2018, 4:06 p.m.

Details

Message ID 1534435591-22542-11-git-send-email-boyuan.zhang@amd.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Mesa

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Commit Message

Zhang, Boyuan Aug. 16, 2018, 4:06 p.m.
From: Boyuan Zhang <boyuan.zhang@amd.com>

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
 src/amd/common/ac_gpu_info.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

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diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 73fc362..a1db3b9 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -99,7 +99,7 @@  bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	struct amdgpu_buffer_size_alignments alignment_info = {};
 	struct amdgpu_heap_info vram, vram_vis, gtt;
 	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
-	struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
+	struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
 	struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
 	struct amdgpu_gds_resource_info gds = {};
 	uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
@@ -199,6 +199,14 @@  bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		}
 	}
 
+	if (info->drm_major == 3 && info->drm_minor >= 17) {
+		r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
+		if (r) {
+			fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
+			return false;
+		}
+	}
+
 	r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
 					&info->me_fw_version,
 					&info->me_fw_feature);
@@ -301,7 +309,8 @@  bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->max_se = amdinfo->num_shader_engines;
 	info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
 	info->has_hw_decode =
-		(uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
+		(uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
+		(vcn_jpeg.available_rings != 0);
 	info->uvd_fw_version =
 		uvd.available_rings ? uvd_version : 0;
 	info->vce_fw_version =
@@ -368,6 +377,7 @@  bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	ib_align = MAX2(ib_align, vce.ib_start_alignment);
 	ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
 	ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
+	ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
        assert(ib_align);
 	info->ib_start_alignment = ib_align;
 

Comments

Reviewed-by: Leo Liu <leo.liu@amd.com>


On 08/16/2018 12:06 PM, boyuan.zhang@amd.com wrote:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> ---
>   src/amd/common/ac_gpu_info.c | 14 ++++++++++++--
>   1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index 73fc362..a1db3b9 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -99,7 +99,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>   	struct amdgpu_buffer_size_alignments alignment_info = {};
>   	struct amdgpu_heap_info vram, vram_vis, gtt;
>   	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
> -	struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
> +	struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
>   	struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
>   	struct amdgpu_gds_resource_info gds = {};
>   	uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
> @@ -199,6 +199,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>   		}
>   	}
>   
> +	if (info->drm_major == 3 && info->drm_minor >= 17) {
> +		r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
> +		if (r) {
> +			fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
> +			return false;
> +		}
> +	}
> +
>   	r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
>   					&info->me_fw_version,
>   					&info->me_fw_feature);
> @@ -301,7 +309,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>   	info->max_se = amdinfo->num_shader_engines;
>   	info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
>   	info->has_hw_decode =
> -		(uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
> +		(uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
> +		(vcn_jpeg.available_rings != 0);
>   	info->uvd_fw_version =
>   		uvd.available_rings ? uvd_version : 0;
>   	info->vce_fw_version =
> @@ -368,6 +377,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>   	ib_align = MAX2(ib_align, vce.ib_start_alignment);
>   	ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
>   	ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
> +	ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
>          assert(ib_align);
>   	info->ib_start_alignment = ib_align;
>