radv/gfx9: update bin sizes

Submitted by Samuel Pitoiset on July 20, 2018, 8:38 a.m.

Details

Message ID 20180720083837.27377-1-samuel.pitoiset@gmail.com
State New
Headers show
Series "radv/gfx9: update bin sizes" ( rev: 1 ) in Mesa

Not browsing as part of any series.

Commit Message

Samuel Pitoiset July 20, 2018, 8:38 a.m.
Based on RadeonSI.

This slightly improves performance when RADV_PERFTEST=binning
is set with Talos on my Vega 56.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
---
 src/amd/vulkan/radv_pipeline.c | 64 +++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 32 deletions(-)

Patch hide | download patch | download mbox

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 27e13a2251..520caabedd 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2261,7 +2261,7 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 				{        0, {128,  128}},
 				{        2, { 64,  128}},
 				{        3, { 32,  128}},
-				{        5, { 16,  128}},
+				{        9, { 16,  128}},
 				{       33, {  0,    0}},
 				{ UINT_MAX, {  0,    0}},
 			},
@@ -2294,7 +2294,7 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 				{        3, { 64,  128}},
 				{        5, { 32,  128}},
 				{        9, { 16,  128}},
-				{       33, {  0,    0}},
+				{       17, {  0,    0}},
 				{ UINT_MAX, {  0,    0}},
 			},
 			{
@@ -2326,8 +2326,8 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 			// One RB / SE
 			{
 				// One shader engine
-				{        0, {128,  256}},
-				{        2, {128,  128}},
+				{        0, { 64,  512}},
+				{        2, { 64,  256}},
 				{        4, { 64,  128}},
 				{        7, { 32,  128}},
 				{       13, { 16,  128}},
@@ -2336,9 +2336,9 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 			},
 			{
 				// Two shader engines
-				{        0, {256,  256}},
-				{        2, {128,  256}},
-				{        4, {128,  128}},
+				{        0, {128,  512}},
+				{        2, { 64,  512}},
+				{        4, { 64,  256}},
 				{        7, { 64,  128}},
 				{       13, { 32,  128}},
 				{       25, { 16,  128}},
@@ -2348,9 +2348,9 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 			{
 				// Four shader engines
 				{        0, {256,  512}},
-				{        2, {256,  256}},
-				{        4, {128,  256}},
-				{        7, {128,  128}},
+				{        2, {128,  512}},
+				{        4, { 64,  512}},
+				{        7, { 64,  256}},
 				{       13, { 64,  128}},
 				{       25, { 16,  128}},
 				{       49, {  0,    0}},
@@ -2361,9 +2361,9 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 			// Two RB / SE
 			{
 				// One shader engine
-				{        0, {256,  256}},
-				{        2, {128,  256}},
-				{        4, {128,  128}},
+				{        0, {128,  512}},
+				{        2, { 64,  512}},
+				{        4, { 64,  256}},
 				{        7, { 64,  128}},
 				{       13, { 32,  128}},
 				{       25, { 16,  128}},
@@ -2372,12 +2372,12 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 			},
 			{
 				// Two shader engines
-				{        0, {256,  512}},
-				{        2, {256,  256}},
-				{        4, {128,  256}},
-				{        7, {128,  128}},
-				{       13, { 64,  128}},
-				{       25, { 32,  128}},
+				{        0, {512,  512}},
+				{        2, {256,  512}},
+				{        4, {128,  512}},
+				{        7, { 64,  512}},
+				{       13, { 64,  256}},
+				{       25, { 64,  128}},
 				{       49, { 16,  128}},
 				{       97, {  0,    0}},
 				{ UINT_MAX, {  0,    0}},
@@ -2386,9 +2386,9 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 				// Four shader engines
 				{        0, {512,  512}},
 				{        2, {256,  512}},
-				{        4, {256,  256}},
-				{        7, {128,  256}},
-				{       13, {128,  128}},
+				{        4, {128,  512}},
+				{        7, { 64,  512}},
+				{       13, { 64,  256}},
 				{       25, { 64,  128}},
 				{       49, { 16,  128}},
 				{       97, {  0,    0}},
@@ -2400,9 +2400,9 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 			{
 				// One shader engine
 				{        0, {256,  512}},
-				{        2, {256,  256}},
-				{        4, {128,  256}},
-				{        7, {128,  128}},
+				{        2, {128,  512}},
+				{        4, { 64,  512}},
+				{        7, { 64,  256}},
 				{       13, { 64,  128}},
 				{       25, { 32,  128}},
 				{       49, { 16,  128}},
@@ -2412,9 +2412,9 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 				// Two shader engines
 				{        0, {512,  512}},
 				{        2, {256,  512}},
-				{        4, {256,  256}},
-				{        7, {128,  256}},
-				{       13, {128,  128}},
+				{        4, {128,  512}},
+				{        7, { 64,  512}},
+				{       13, { 64,  256}},
 				{       25, { 64,  128}},
 				{       49, { 32,  128}},
 				{       97, { 16,  128}},
@@ -2424,10 +2424,10 @@  radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
 				// Four shader engines
 				{        0, {512,  512}},
 				{        4, {256,  512}},
-				{        7, {256,  256}},
-				{       13, {128,  256}},
-				{       25, {128,  128}},
-				{       49, { 64,  128}},
+				{        7, {128,  512}},
+				{       13, { 64,  512}},
+				{       25, { 32,  512}},
+				{       49, { 32,  256}},
 				{       97, { 16,  128}},
 				{ UINT_MAX, {  0,    0}},
 			},