[07/21] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll

Submitted by Sean Paul on July 9, 2018, 5:31 p.m.

Details

Message ID 20180709173200.238457-8-seanpaul@chromium.org
State New
Headers show
Series "drm/msm: Add support for SDM845 Display Processing Unit (DPU)" ( rev: 3 2 1 ) in DRI devel

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Commit Message

Sean Paul July 9, 2018, 5:31 p.m.
From: Rajesh Yadav <ryadav@codeaurora.org>

postdiv_lock spinlock was used before initialization
for 10nm pll. It causes following spin_bug:
	"BUG: spinlock bad magic on CPU#0".
Initialize spinlock before its usage.

Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 2 ++
 1 file changed, 2 insertions(+)

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diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index c4c37a7df637..4c03f0b7343e 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -798,6 +798,8 @@  struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
 		return ERR_PTR(-ENOMEM);
 	}
 
+	spin_lock_init(&pll_10nm->postdiv_lock);
+
 	pll = &pll_10nm->base;
 	pll->min_rate = 1000000000UL;
 	pll->max_rate = 3500000000UL;

Comments

On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
> From: Rajesh Yadav <ryadav@codeaurora.org>
> 
> postdiv_lock spinlock was used before initialization
> for 10nm pll. It causes following spin_bug:
> 	"BUG: spinlock bad magic on CPU#0".
> Initialize spinlock before its usage.

Reviewed-by: Archit Taneja <architt@codeaurora.org>

> 
> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
> Signed-off-by: Sean Paul <seanpaul@chromium.org>
> ---
>   drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> index c4c37a7df637..4c03f0b7343e 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> @@ -798,6 +798,8 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
>   		return ERR_PTR(-ENOMEM);
>   	}
>   
> +	spin_lock_init(&pll_10nm->postdiv_lock);
> +
>   	pll = &pll_10nm->base;
>   	pll->min_rate = 1000000000UL;
>   	pll->max_rate = 3500000000UL;
>