[3/4] radv: add support for non-inverted conditional rendering

Submitted by Samuel Pitoiset on July 9, 2018, 9:42 a.m.

Details

Message ID 20180709094233.31059-3-samuel.pitoiset@gmail.com
State Accepted
Headers show
Series "Series without cover letter" ( rev: 3 2 1 ) in Mesa

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Commit Message

Samuel Pitoiset July 9, 2018, 9:42 a.m.
By default, our internal rendering commands are discarded
only if the predicate is non-zero (ie. DRAW_VISIBLE). But
VK_EXT_conditional_rendering also allows to discard commands
when the predicate is zero, which means we have to use a
different flag.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
---
 src/amd/vulkan/radv_meta_fast_clear.c |  2 +-
 src/amd/vulkan/radv_private.h         |  3 ++-
 src/amd/vulkan/si_cmd_buffer.c        | 17 ++++++++++++++---
 3 files changed, 17 insertions(+), 5 deletions(-)

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diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index 136557080d..d3cd445d97 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -571,7 +571,7 @@  radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer,
 		va += image->dcc_pred_offset;
 	}
 
-	si_emit_set_predication_state(cmd_buffer, va);
+	si_emit_set_predication_state(cmd_buffer, true, va);
 }
 
 /**
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 4e4b3a6037..b7cebafe48 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1083,7 +1083,8 @@  void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
 			    bool is_mec,
 			    enum radv_cmd_flush_bits flush_bits);
 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
-void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
+void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
+				   bool inverted, uint64_t va);
 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
 			   uint64_t src_va, uint64_t dest_va,
 			   uint64_t size);
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 454fd8c39c..3363f99af3 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -986,12 +986,23 @@  si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
 
 /* sets the CP predication state using a boolean stored at va */
 void
-si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
+si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
+			      bool inverted, uint64_t va)
 {
 	uint32_t op = 0;
 
-	if (va)
-		op = PRED_OP(PREDICATION_OP_BOOL64) | PREDICATION_DRAW_VISIBLE;
+	if (va) {
+		op = PRED_OP(PREDICATION_OP_BOOL64);
+
+		/* By default, our internal rendering commands are discarded
+		 * only if the predicate is non-zero (ie. DRAW_VISIBLE). But
+		 * VK_EXT_conditional_rendering also allows to discard commands
+		 * when the predicate is zero, which means we have to use a
+		 * different flag.
+		 */
+		op |= inverted ? PREDICATION_DRAW_VISIBLE :
+				 PREDICATION_DRAW_NOT_VISIBLE;
+	}
 	if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 		radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
 		radeon_emit(cmd_buffer->cs, op);