[v2,1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10

Submitted by Michel Thierry on June 4, 2018, 11:32 p.m.

Details

Message ID 20180604233250.609-1-michel.thierry@intel.com
State Accepted
Commit 9904b1560e4a2e7c956004f9843939e23d84cd7b
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX

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Commit Message

Michel Thierry June 4, 2018, 11:32 p.m.
The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
context hw id in GEN8-10, so use them and have one less thing to
maintain in the unlikely case we change the descriptor sw fields.

v2: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel)

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_perf.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a6c8d61add0c..6aba30cb40ea 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1279,9 +1279,12 @@  static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
 			i915->perf.oa.specific_ctx_id_mask =
 				(1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
 		} else {
-			i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
 			i915->perf.oa.specific_ctx_id_mask =
 				(1U << GEN8_CTX_ID_WIDTH) - 1;
+			i915->perf.oa.specific_ctx_id =
+				upper_32_bits(ce->lrc_desc);
+			i915->perf.oa.specific_ctx_id &=
+				i915->perf.oa.specific_ctx_id_mask;
 		}
 		break;
 

Comments

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

On 05/06/18 00:32, Michel Thierry wrote:
> The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
> context hw id in GEN8-10, so use them and have one less thing to
> maintain in the unlikely case we change the descriptor sw fields.
>
> v2: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel)
>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/i915_perf.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index a6c8d61add0c..6aba30cb40ea 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1279,9 +1279,12 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
>   			i915->perf.oa.specific_ctx_id_mask =
>   				(1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
>   		} else {
> -			i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
>   			i915->perf.oa.specific_ctx_id_mask =
>   				(1U << GEN8_CTX_ID_WIDTH) - 1;
> +			i915->perf.oa.specific_ctx_id =
> +				upper_32_bits(ce->lrc_desc);
> +			i915->perf.oa.specific_ctx_id &=
> +				i915->perf.oa.specific_ctx_id_mask;
>   		}
>   		break;
>
Thanks Michel, both patches pushed.

-
Lionel

On 05/06/18 00:32, Michel Thierry wrote:
> The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
> context hw id in GEN8-10, so use them and have one less thing to
> maintain in the unlikely case we change the descriptor sw fields.
>
> v2: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel)
>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/i915_perf.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index a6c8d61add0c..6aba30cb40ea 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1279,9 +1279,12 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
>   			i915->perf.oa.specific_ctx_id_mask =
>   				(1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
>   		} else {
> -			i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
>   			i915->perf.oa.specific_ctx_id_mask =
>   				(1U << GEN8_CTX_ID_WIDTH) - 1;
> +			i915->perf.oa.specific_ctx_id =
> +				upper_32_bits(ce->lrc_desc);
> +			i915->perf.oa.specific_ctx_id &=
> +				i915->perf.oa.specific_ctx_id_mask;
>   		}
>   		break;
>