drm/i915/perf: fix gen11 engine class shift

Submitted by Michel Thierry on June 4, 2018, 6:17 p.m.

Details

Message ID 20180604181724.3658-1-michel.thierry@intel.com
State New
Headers show
Series "drm/i915/perf: fix gen11 engine class shift" ( rev: 1 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Michel Thierry June 4, 2018, 6:17 p.m.
Use the correct engine class shift value while storing the ctx hw id.
Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix
ctx_id read with GuC & ICL").

Apologies for not spotting this in the original review, the
specific_ctx_id_mask is correct, only the specific_ctx_id had this
problem.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_perf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a6c8d61add0c..c15c7b0fb482 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1291,7 +1291,7 @@  static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
 		i915->perf.oa.specific_ctx_id =
 			stream->ctx->hw_id << (GEN11_SW_CTX_ID_SHIFT - 32) |
 			engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
-			engine->class << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
+			engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
 		i915->perf.oa.specific_ctx_id_mask =
 			((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
 			((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |

Comments

Arg, I'm pretty sure I've run into that same issue before.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

On 04/06/18 19:17, Michel Thierry wrote:
> Use the correct engine class shift value while storing the ctx hw id.
> Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix
> ctx_id read with GuC & ICL").
>
> Apologies for not spotting this in the original review, the
> specific_ctx_id_mask is correct, only the specific_ctx_id had this
> problem.
Fixes: 61d5676b5561d6 ("drm/i915/perf: fix ctx_id read with GuC & ICL")
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/i915_perf.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index a6c8d61add0c..c15c7b0fb482 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1291,7 +1291,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
>   		i915->perf.oa.specific_ctx_id =
>   			stream->ctx->hw_id << (GEN11_SW_CTX_ID_SHIFT - 32) |
>   			engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
> -			engine->class << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
> +			engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
>   		i915->perf.oa.specific_ctx_id_mask =
>   			((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
>   			((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
On 06/04/2018 11:58 AM, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/perf: fix gen11 engine class shift
> URL   : https://patchwork.freedesktop.org/series/44216/
> State : failure
> 
> == Summary ==
> 
> = CI Bug Log - changes from CI_DRM_4277 -> Patchwork_9187 =
> 
> == Summary - FAILURE ==
> 
>    Serious unknown changes coming with Patchwork_9187 absolutely need to be
>    verified manually.
>    
>    If you think the reported changes have nothing to do with the changes
>    introduced in Patchwork_9187, please notify your bug team to allow them
>    to document this new failure mode, which will reduce false positives in CI.
> 
>    External URL: https://patchwork.freedesktop.org/api/1.0/series/44216/revisions/1/mbox/
> 
> == Possible new issues ==
> 
>    Here are the unknown changes that may have been introduced in Patchwork_9187:
> 
>    === IGT changes ===
> 
>      ==== Possible regressions ====
> 
>      igt@gem_exec_suspend@basic-s4-devices:
>        fi-hsw-peppy:       PASS -> FAIL

I'm pretty confident the gen11 oa engine class cannot break hsw's s4.

> 
>      
>      ==== Warnings ====
> 
>      igt@gem_exec_gttfill@basic:
>        fi-pnv-d510:        SKIP -> PASS
> 
>      
> == Known issues ==
> 
>    Here are the changes found in Patchwork_9187 that come from known issues:
> 
>    === IGT changes ===
> 
>      ==== Issues hit ====
> 
>      igt@gem_exec_flush@basic-uc-prw-default:
>        fi-glk-j4005:       PASS -> DMESG-WARN (fdo#105719)
> 
>      igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
>        fi-cnl-psr:         PASS -> DMESG-WARN (fdo#104951)
> 
>      igt@prime_vgem@basic-fence-flip:
>        fi-ilk-650:         PASS -> FAIL (fdo#104008)
> 
>      
>    fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
>    fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
>    fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
> 
> 
> == Participating hosts (42 -> 37) ==
> 
>    Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq fi-hsw-4200u
> 
> 
> == Build changes ==
> 
>      * Linux: CI_DRM_4277 -> Patchwork_9187
> 
>    CI_DRM_4277: 2309ca0c3ab113e1e760045e230576e0ab4a88e2 @ git://anongit.freedesktop.org/gfx-ci/linux
>    IGT_4505: 8a8f0271a71e2e0d2a2caa4d41f4ad1d9c89670e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>    Patchwork_9187: 41f29e32d8d81a18e54211088ca624462c8b9e70 @ git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> 41f29e32d8d8 drm/i915/perf: fix gen11 engine class shift
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9187/issues.html
>
On 04/06/18 20:26, Michel Thierry wrote:
> On 06/04/2018 11:58 AM, Patchwork wrote:
>> == Series Details ==
>>
>> Series: drm/i915/perf: fix gen11 engine class shift
>> URL   : https://patchwork.freedesktop.org/series/44216/
>> State : failure
>>
>> == Summary ==
>>
>> = CI Bug Log - changes from CI_DRM_4277 -> Patchwork_9187 =
>>
>> == Summary - FAILURE ==
>>
>>    Serious unknown changes coming with Patchwork_9187 absolutely need 
>> to be
>>    verified manually.
>>       If you think the reported changes have nothing to do with the 
>> changes
>>    introduced in Patchwork_9187, please notify your bug team to allow 
>> them
>>    to document this new failure mode, which will reduce false 
>> positives in CI.
>>
>>    External URL: 
>> https://patchwork.freedesktop.org/api/1.0/series/44216/revisions/1/mbox/
>>
>> == Possible new issues ==
>>
>>    Here are the unknown changes that may have been introduced in 
>> Patchwork_9187:
>>
>>    === IGT changes ===
>>
>>      ==== Possible regressions ====
>>
>>      igt@gem_exec_suspend@basic-s4-devices:
>>        fi-hsw-peppy:       PASS -> FAIL
>
> I'm pretty confident the gen11 oa engine class cannot break hsw's s4.

Yep, the worse that could happen with your patch is a failure on the 
perf tests.

>
>>
>>           ==== Warnings ====
>>
>>      igt@gem_exec_gttfill@basic:
>>        fi-pnv-d510:        SKIP -> PASS
>>
>>      == Known issues ==
>>
>>    Here are the changes found in Patchwork_9187 that come from known 
>> issues:
>>
>>    === IGT changes ===
>>
>>      ==== Issues hit ====
>>
>>      igt@gem_exec_flush@basic-uc-prw-default:
>>        fi-glk-j4005:       PASS -> DMESG-WARN (fdo#105719)
>>
>>      igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
>>        fi-cnl-psr:         PASS -> DMESG-WARN (fdo#104951)
>>
>>      igt@prime_vgem@basic-fence-flip:
>>        fi-ilk-650:         PASS -> FAIL (fdo#104008)
>>
>>         fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
>>    fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
>>    fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
>>
>>
>> == Participating hosts (42 -> 37) ==
>>
>>    Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks 
>> fi-skl-6700hq fi-hsw-4200u
>>
>>
>> == Build changes ==
>>
>>      * Linux: CI_DRM_4277 -> Patchwork_9187
>>
>>    CI_DRM_4277: 2309ca0c3ab113e1e760045e230576e0ab4a88e2 @ 
>> git://anongit.freedesktop.org/gfx-ci/linux
>>    IGT_4505: 8a8f0271a71e2e0d2a2caa4d41f4ad1d9c89670e @ 
>> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>>    Patchwork_9187: 41f29e32d8d81a18e54211088ca624462c8b9e70 @ 
>> git://anongit.freedesktop.org/gfx-ci/linux
>>
>>
>> == Linux commits ==
>>
>> 41f29e32d8d8 drm/i915/perf: fix gen11 engine class shift
>>
>> == Logs ==
>>
>> For more details see: 
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9187/issues.html
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Michel Thierry (2018-06-04 19:17:24)
> Use the correct engine class shift value while storing the ctx hw id.
> Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix
> ctx_id read with GuC & ICL").
> 
> Apologies for not spotting this in the original review, the
> specific_ctx_id_mask is correct, only the specific_ctx_id had this
> problem.
> 
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_perf.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index a6c8d61add0c..c15c7b0fb482 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1291,7 +1291,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
>                 i915->perf.oa.specific_ctx_id =
>                         stream->ctx->hw_id << (GEN11_SW_CTX_ID_SHIFT - 32) |
>                         engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
> -                       engine->class << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
> +                       engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);

Hmm, isn't this upper_32_bits(ce->lrc_desc) ?
-Chris
On 6/4/2018 2:03 PM, Chris Wilson wrote:
> Quoting Michel Thierry (2018-06-04 19:17:24)
>> Use the correct engine class shift value while storing the ctx hw id.
>> Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix
>> ctx_id read with GuC & ICL").
>>
>> Apologies for not spotting this in the original review, the
>> specific_ctx_id_mask is correct, only the specific_ctx_id had this
>> problem.
>>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>>   drivers/gpu/drm/i915/i915_perf.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> index a6c8d61add0c..c15c7b0fb482 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -1291,7 +1291,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
>>                  i915->perf.oa.specific_ctx_id =
>>                          stream->ctx->hw_id << (GEN11_SW_CTX_ID_SHIFT - 32) |
>>                          engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
>> -                       engine->class << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
>> +                       engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
> 
> Hmm, isn't this upper_32_bits(ce->lrc_desc) ?

True, it is (and since the lrc_desc is already available, we can argue 
it is also true for !guc in Gen8-10).

I'll change it.

Thanks,

-Michel