[03/14] radeonsi: record CLIPVERTEX output usage properly for compatibility profiles

Submitted by Marek Olšák on June 1, 2018, 5:21 a.m.

Details

Message ID 20180601052122.27421-4-maraeo@gmail.com
State New
Headers show
Series "RadeonSI: New batch of improvements" ( rev: 1 ) in Mesa

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Commit Message

Marek Olšák June 1, 2018, 5:21 a.m.
From: Marek Olšák <marek.olsak@amd.com>

This was missed when adding CLIPVERTEX support into GS & tess.
---
 src/gallium/drivers/radeonsi/si_state_shaders.c | 1 -
 1 file changed, 1 deletion(-)

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diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 707bb4187ef..74fe2c1ffc9 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2099,21 +2099,20 @@  static void *si_create_shader_selector(struct pipe_context *ctx,
 				/* don't process indices the function can't handle */
 				if (index >= SI_MAX_IO_GENERIC)
 					break;
 				/* fall through */
 			default:
 				sel->outputs_written |=
 					1ull << si_shader_io_get_unique_index(name, index, false);
 				sel->outputs_written_before_ps |=
 					1ull << si_shader_io_get_unique_index(name, index, true);
 				break;
-			case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
 			case TGSI_SEMANTIC_EDGEFLAG:
 				break;
 			}
 		}
 		sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
 
 		/* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
 		 * conflicts, i.e. each vertex will start at a different bank.
 		 */
 		if (sctx->chip_class >= GFX9)