[BACKPORT,v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

Submitted by Michel Thierry on May 14, 2018, 4:54 p.m.

Details

Message ID 20180514165445.9198-1-michel.thierry@intel.com
State Accepted
Commit b579f924a90f42fa561afd8201514fc216b71949
Headers show
Series "drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk" ( rev: 2 ) in Intel GFX

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Commit Message

Michel Thierry May 14, 2018, 4:54 p.m.
Factor in clear values wherever required while updating destination
min/max.

References: HSDES#1604444184
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: mesa-dev@lists.freedesktop.org
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
Cc: stable@vger.kernel.org
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        | 3 +++
 drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
 2 files changed, 7 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e6a8c0ee7df1..8a69a9275e28 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7326,6 +7326,9 @@  enum {
 #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
 #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
 
+#define GEN9_WM_CHICKEN3			_MMIO(0x5588)
+#define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
+
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
 #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 4ba139c27fba..f7c25828d3bb 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1149,6 +1149,10 @@  static int gen9_init_workarounds(struct intel_engine_cs *engine)
 	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 
+	/* WaClearHIZ_WM_CHICKEN3:bxt,glk */
+	if (IS_GEN9_LP(dev_priv))
+		WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
+
 	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
 	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
 	if (ret)

Comments

On Mon, 14 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
> Factor in clear values wherever required while updating destination
> min/max.

Hi Michel, please elaborate what the intention here is.

BR,
Jani.



>
> References: HSDES#1604444184
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Cc: mesa-dev@lists.freedesktop.org
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
> Cc: stable@vger.kernel.org
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h        | 3 +++
>  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e6a8c0ee7df1..8a69a9275e28 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7326,6 +7326,9 @@ enum {
>  #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
>  #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
>  
> +#define GEN9_WM_CHICKEN3			_MMIO(0x5588)
> +#define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
> +
>  /* WaCatErrorRejectionIssue */
>  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
>  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 4ba139c27fba..f7c25828d3bb 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>  			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>  
> +	/* WaClearHIZ_WM_CHICKEN3:bxt,glk */
> +	if (IS_GEN9_LP(dev_priv))
> +		WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
> +
>  	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>  	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>  	if (ret)
On 5/15/2018 10:13 AM, Jani Nikula wrote:
> On Mon, 14 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
>> Factor in clear values wherever required while updating destination
>> min/max.
> 
> Hi Michel, please elaborate what the intention here is.
> 

Hi Jani, isn't the intention of all the workarounds to prevent gpu hangs?

> BR,
> Jani.
> 
> 
> 
>>
>> References: HSDES#1604444184
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> Cc: mesa-dev@lists.freedesktop.org
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
>> Cc: stable@vger.kernel.org
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h        | 3 +++
>>   drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>>   2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e6a8c0ee7df1..8a69a9275e28 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7326,6 +7326,9 @@ enum {
>>   #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
>>   #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
>>   
>> +#define GEN9_WM_CHICKEN3			_MMIO(0x5588)
>> +#define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
>> +
>>   /* WaCatErrorRejectionIssue */
>>   #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
>>   #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index 4ba139c27fba..f7c25828d3bb 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>>   	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>>   			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>>   
>> +	/* WaClearHIZ_WM_CHICKEN3:bxt,glk */
>> +	if (IS_GEN9_LP(dev_priv))
>> +		WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
>> +
>>   	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>>   	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>>   	if (ret)
>
On Tue, 15 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
> On 5/15/2018 10:13 AM, Jani Nikula wrote:
>> On Mon, 14 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
>>> Factor in clear values wherever required while updating destination
>>> min/max.
>> 
>> Hi Michel, please elaborate what the intention here is.
>> 
>
> Hi Jani, isn't the intention of all the workarounds to prevent gpu
> hangs?

Err, sorry for the riddles, I meant with [BACKPORT v4.17-rc5] etc. :)

Is this in dinq already? Commit id?

BR,
Jani.



>
>> BR,
>> Jani.
>> 
>> 
>> 
>>>
>>> References: HSDES#1604444184
>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>> Cc: mesa-dev@lists.freedesktop.org
>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
>>> Cc: stable@vger.kernel.org
>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_reg.h        | 3 +++
>>>   drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>>>   2 files changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index e6a8c0ee7df1..8a69a9275e28 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -7326,6 +7326,9 @@ enum {
>>>   #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
>>>   #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
>>>   
>>> +#define GEN9_WM_CHICKEN3			_MMIO(0x5588)
>>> +#define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
>>> +
>>>   /* WaCatErrorRejectionIssue */
>>>   #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
>>>   #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
>>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>>> index 4ba139c27fba..f7c25828d3bb 100644
>>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>>> @@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>>>   	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>>>   			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>>>   
>>> +	/* WaClearHIZ_WM_CHICKEN3:bxt,glk */
>>> +	if (IS_GEN9_LP(dev_priv))
>>> +		WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
>>> +
>>>   	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>>>   	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>>>   	if (ret)
>>
On 5/15/2018 11:17 AM, Jani Nikula wrote:
> On Tue, 15 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
>> On 5/15/2018 10:13 AM, Jani Nikula wrote:
>>> On Mon, 14 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
>>>> Factor in clear values wherever required while updating destination
>>>> min/max.
>>>
>>> Hi Michel, please elaborate what the intention here is.
>>>
>>
>> Hi Jani, isn't the intention of all the workarounds to prevent gpu
>> hangs?
> 
> Err, sorry for the riddles, I meant with [BACKPORT v4.17-rc5] etc. :)
> 
No worries,

> Is this in dinq already? Commit id?
It was merged only a couple of days ago,

https://cgit.freedesktop.org/drm-tip/commit/?id=0c79f9cb77eae28d48a4f9fc1b3341aacbbd260c

Joonas asked me to backport it (stable doesn't have the 
intel_workarounds refactor yet).

> 
> BR,
> Jani.
> 
> 
> 
>>
>>> BR,
>>> Jani.
>>>
>>>
>>>
>>>>
>>>> References: HSDES#1604444184
>>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>>> Cc: mesa-dev@lists.freedesktop.org
>>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>>> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>>> Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
>>>> Cc: stable@vger.kernel.org
>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_reg.h        | 3 +++
>>>>    drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>>>>    2 files changed, 7 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index e6a8c0ee7df1..8a69a9275e28 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -7326,6 +7326,9 @@ enum {
>>>>    #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
>>>>    #define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)
>>>>    
>>>> +#define GEN9_WM_CHICKEN3			_MMIO(0x5588)
>>>> +#define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
>>>> +
>>>>    /* WaCatErrorRejectionIssue */
>>>>    #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
>>>>    #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
>>>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>>>> index 4ba139c27fba..f7c25828d3bb 100644
>>>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>>>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>>>> @@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>>>>    	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>>>>    			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>>>>    
>>>> +	/* WaClearHIZ_WM_CHICKEN3:bxt,glk */
>>>> +	if (IS_GEN9_LP(dev_priv))
>>>> +		WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
>>>> +
>>>>    	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>>>>    	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>>>>    	if (ret)
>>>
>