[v2,2/4] drm/i915/gvt: let NOPID be the default value of force_to_nonpriv registers

Submitted by Zhao, Yan Y on May 7, 2018, 7:13 a.m.

Details

Message ID 1525677188-8498-1-git-send-email-yan.y.zhao@intel.com
State New
Headers show
Series "refactor the force-nonpriv handler" ( rev: 1 ) in Intel GVT devel

Not browsing as part of any series.

Commit Message

Zhao, Yan Y May 7, 2018, 7:13 a.m.
Each ring has a NOPID register and currently they are regarded as default
value of force_to_nonpriv registers in guest drivers

Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c |  9 ++++++++-
 drivers/gpu/drm/i915/gvt/handlers.c   | 22 ++++++++++++++--------
 2 files changed, 22 insertions(+), 9 deletions(-)

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diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index b54b1f3..4f36e2f 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -820,8 +820,15 @@  static int force_nonpriv_reg_handler(struct parser_exec_state *s,
 {
 	struct intel_gvt *gvt = s->vgpu->gvt;
 	unsigned int data = cmd_val(s, index + 1);
+	u32 ring_base;
+	u32 nopid;
+	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
+
+	ring_base = dev_priv->engine[s->ring_id]->mmio_base;
+	nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
 
-	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
+	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
+			data != nopid) {
 		gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
 			offset, data);
 		return -EPERM;
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index f1a5016..08f96f9 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -477,21 +477,27 @@  static int force_nonpriv_write(struct intel_vgpu *vgpu,
 	unsigned int offset, void *p_data, unsigned int bytes)
 {
 	u32 reg_nonpriv = *(u32 *)p_data;
+	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
+	u32 ring_base;
+	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 	int ret = -EINVAL;
 
-	if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {
-		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
-			vgpu->id, offset, bytes);
+	if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {
+		gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",
+			vgpu->id, ring_id, offset, bytes);
 		return ret;
 	}
 
-	if (in_whitelist(reg_nonpriv)) {
+	ring_base = dev_priv->engine[ring_id]->mmio_base;
+
+	if (in_whitelist(reg_nonpriv) ||
+		reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
 		ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
 			bytes);
-	} else {
-		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",
-			vgpu->id, reg_nonpriv);
-	}
+	} else
+		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
+			vgpu->id, reg_nonpriv, offset);
+
 	return ret;
 }
 

Comments

On 2018.05.07 15:13:08 +0800, Zhao Yan wrote:
> Each ring has a NOPID register and currently they are regarded as default
> value of force_to_nonpriv registers in guest drivers
> 
> Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
> ---

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>

>  drivers/gpu/drm/i915/gvt/cmd_parser.c |  9 ++++++++-
>  drivers/gpu/drm/i915/gvt/handlers.c   | 22 ++++++++++++++--------
>  2 files changed, 22 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index b54b1f3..4f36e2f 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -820,8 +820,15 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s,
>  {
>  	struct intel_gvt *gvt = s->vgpu->gvt;
>  	unsigned int data = cmd_val(s, index + 1);
> +	u32 ring_base;
> +	u32 nopid;
> +	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
> +
> +	ring_base = dev_priv->engine[s->ring_id]->mmio_base;
> +	nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
>  
> -	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {
> +	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
> +			data != nopid) {
>  		gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
>  			offset, data);
>  		return -EPERM;
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index f1a5016..08f96f9 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -477,21 +477,27 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu,
>  	unsigned int offset, void *p_data, unsigned int bytes)
>  {
>  	u32 reg_nonpriv = *(u32 *)p_data;
> +	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
> +	u32 ring_base;
> +	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
>  	int ret = -EINVAL;
>  
> -	if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {
> -		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
> -			vgpu->id, offset, bytes);
> +	if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {
> +		gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",
> +			vgpu->id, ring_id, offset, bytes);
>  		return ret;
>  	}
>  
> -	if (in_whitelist(reg_nonpriv)) {
> +	ring_base = dev_priv->engine[ring_id]->mmio_base;
> +
> +	if (in_whitelist(reg_nonpriv) ||
> +		reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {
>  		ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
>  			bytes);
> -	} else {
> -		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",
> -			vgpu->id, reg_nonpriv);
> -	}
> +	} else
> +		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
> +			vgpu->id, reg_nonpriv, offset);
> +
>  	return ret;
>  }
>  
> -- 
> 1.9.1
> 
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