[v2,1/4] drm/i915/gvt: adds force_to_nonpriv registers for all rings

Submitted by Zhao, Yan Y on May 7, 2018, 7:12 a.m.

Details

Message ID 1525677179-8460-1-git-send-email-yan.y.zhao@intel.com
State New
Headers show
Series "refactor the force-nonpriv handler" ( rev: 1 ) in Intel GVT devel

Not browsing as part of any series.

Commit Message

Zhao, Yan Y May 7, 2018, 7:12 a.m.
Not only render ring, each ring has 12 force_to_nonpriv registers.
Add those registers into the force_to_nonpriv handling range.

Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 ++++++---
 drivers/gpu/drm/i915/gvt/handlers.c   | 4 +++-
 2 files changed, 9 insertions(+), 4 deletions(-)

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diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index d895069..b54b1f3 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -807,9 +807,12 @@  static bool is_shadowed_mmio(unsigned int offset)
 	return ret;
 }
 
-static inline bool is_force_nonpriv_mmio(unsigned int offset)
+static bool is_force_nonpriv_mmio(struct parser_exec_state *s,
+		unsigned int offset)
 {
-	return (offset >= 0x24d0 && offset < 0x2500);
+	u32 base = s->vgpu->gvt->dev_priv->engine[s->ring_id]->mmio_base;
+
+	return (offset >= (base + 0x4d0) && offset < (base + 0x500));
 }
 
 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
@@ -868,7 +871,7 @@  static int cmd_reg_handler(struct parser_exec_state *s,
 	    mocs_cmd_reg_handler(s, offset, index))
 		return -EINVAL;
 
-	if (is_force_nonpriv_mmio(offset) &&
+	if (is_force_nonpriv_mmio(s, offset) &&
 		force_nonpriv_reg_handler(s, offset, index))
 		return -EPERM;
 
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index b77adcc..f1a5016 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2594,8 +2594,10 @@  static int init_broadwell_mmio_info(struct intel_gvt *gvt)
 	MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
 	MMIO_D(_MMIO(0xb110), D_BDW);
 
-	MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
+#define RING_REG(base) _MMIO((base) + 0x4d0)
+	MMIO_RING_F(RING_REG, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
 		NULL, force_nonpriv_write);
+#undef RING_REG
 
 	MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
 	MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);

Comments

On 2018.05.07 15:12:59 +0800, Zhao Yan wrote:
> Not only render ring, each ring has 12 force_to_nonpriv registers.
> Add those registers into the force_to_nonpriv handling range.
> 
> Signed-off-by: Zhao Yan <yan.y.zhao@intel.com>
> ---

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>

>  drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 ++++++---
>  drivers/gpu/drm/i915/gvt/handlers.c   | 4 +++-
>  2 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index d895069..b54b1f3 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -807,9 +807,12 @@ static bool is_shadowed_mmio(unsigned int offset)
>  	return ret;
>  }
>  
> -static inline bool is_force_nonpriv_mmio(unsigned int offset)
> +static bool is_force_nonpriv_mmio(struct parser_exec_state *s,
> +		unsigned int offset)
>  {
> -	return (offset >= 0x24d0 && offset < 0x2500);
> +	u32 base = s->vgpu->gvt->dev_priv->engine[s->ring_id]->mmio_base;
> +
> +	return (offset >= (base + 0x4d0) && offset < (base + 0x500));
>  }
>  
>  static int force_nonpriv_reg_handler(struct parser_exec_state *s,
> @@ -868,7 +871,7 @@ static int cmd_reg_handler(struct parser_exec_state *s,
>  	    mocs_cmd_reg_handler(s, offset, index))
>  		return -EINVAL;
>  
> -	if (is_force_nonpriv_mmio(offset) &&
> +	if (is_force_nonpriv_mmio(s, offset) &&
>  		force_nonpriv_reg_handler(s, offset, index))
>  		return -EPERM;
>  
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index b77adcc..f1a5016 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2594,8 +2594,10 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
>  	MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
>  	MMIO_D(_MMIO(0xb110), D_BDW);
>  
> -	MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
> +#define RING_REG(base) _MMIO((base) + 0x4d0)
> +	MMIO_RING_F(RING_REG, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
>  		NULL, force_nonpriv_write);
> +#undef RING_REG
>  
>  	MMIO_D(_MMIO(0x44484), D_BDW_PLUS);
>  	MMIO_D(_MMIO(0x4448c), D_BDW_PLUS);
> -- 
> 1.9.1
> 
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