drm/amdgpu: limit reg_write_reg_wait workaround to SRIOV

Submitted by Deng, Emily on April 18, 2018, 1:59 a.m.

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Message ID CY4PR12MB1125DD21F2A4E63E2ABE43928FB60@CY4PR12MB1125.namprd12.prod.outlook.com
State New
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Series "drm/amdgpu: limit reg_write_reg_wait workaround to SRIOV" ( rev: 3 ) in AMD X.Org drivers

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Commit Message

Deng, Emily April 18, 2018, 1:59 a.m.
Hi all,
Does this actually work on SR-IOV? Or does it just seem to but nothing bad happens because we get a GPU reset on a world switch?
I honestly don't know. I think that SR-IOV uses a specialized firmware where this packet has a different meaning.

But the real fix would be to get the RLC firmware fix to not reinitialize those regs to zero on world switch.
[Emily]Yes, it actually works on SR-IOV, it fixes lots of engine hang issue.

Best Wishes,
Emily Deng
From: Christian K├Ânig [mailto:ckoenig.leichtzumerken@gmail.com]
Sent: Tuesday, April 17, 2018 11:27 PM
To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>
Subject: Re: [PATCH] drm/amdgpu: limit reg_write_reg_wait workaround to SRIOV

Does this actually work on SR-IOV? Or does it just seem to but nothing bad happens because we get a GPU reset on a world switch?
I honestly don't know. I think that SR-IOV uses a specialized firmware where this packet has a different meaning.

But the real fix would be to get the RLC firmware fix to not reinitialize those regs to zero on world switch.

Christian.

Am 17.04.2018 um 16:02 schrieb Deucher, Alexander:

Does this actually work on SR-IOV?  Or does it just seem to but nothing bad happens because we get a GPU reset on a world switch?  The behavior of this packet should be the same as SDMA and that definitely doesn't work.  I don't see why this would be any different.



Acked-by: Alex Deucher <alexander.deucher@amd.com><mailto:alexander.deucher@amd.com>



Alex

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 583f6f616dd3..5329d7e5fb71 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4144,7 +4144,12 @@  static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
 {
         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);

-       gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, ref, mask, 0x20);
+       if (amdgpu_sriov_vf(adev))
+               gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
+                                     ref, mask, 0x20);
+       else
+               amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
+                                                          ref, mask);
 }

 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,