[02/22] drm/i915/icl: Enable Sampler DFR

Submitted by Oscar Mateo Lozano on April 13, 2018, 4 p.m.

Details

Message ID 1523635265-9287-2-git-send-email-oscar.mateo@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX

Browsing this patch as part of:
"Series without cover letter" rev 1 in Intel GFX
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Commit Message

Oscar Mateo Lozano April 13, 2018, 4 p.m.
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring

Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Praveen Paneri <praveen.paneri@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 7 insertions(+)

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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f2ee225..4b7e6bc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8218,6 +8218,9 @@  enum {
 #define GEN8_GARBCNTL                   _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
 
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
+#define   DFR_DISABLE			(1 << 9)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 8c2d17c..34a0b56 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -692,6 +692,10 @@  static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(_3D_CHICKEN3,
 		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
 
+	/* This is not an Wa. Enable to reduce Sampler power */
+	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+
 	/* WaInPlaceDecompressionHang:icl */
 	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
 					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));

Comments

On 4/13/2018 9:30 PM, Oscar Mateo wrote:
> Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> power by dynamically changing its clock frequency in low-throughput
> conditions. This patches enables it by default on Gen11.
>
> v2: Wrong operation to clear the bit (Praveen)
> v3: Rebased on top of the WA refactoring
>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Praveen Paneri <praveen.paneri@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>   drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
>   2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f2ee225..4b7e6bc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8218,6 +8218,9 @@ enum {
>   #define GEN8_GARBCNTL                   _MMIO(0xB004)
>   #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>   
> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
> +#define   DFR_DISABLE			(1 << 9)
> +
>   /* IVYBRIDGE DPF */
>   #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>   #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 8c2d17c..34a0b56 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -692,6 +692,10 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>   	I915_WRITE(_3D_CHICKEN3,
>   		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>   
> +	/* This is not an Wa. Enable to reduce Sampler power */
> +	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> +		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
> +
>   	/* WaInPlaceDecompressionHang:icl */
>   	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
>   					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));