[21/55] radeonsi: make radeon_add_to_buffer_list_check_mem be gfx-only

Submitted by Marek Olšák on April 2, 2018, 4:08 a.m.

Details

Message ID 1522642128-15348-22-git-send-email-maraeo@gmail.com
State Accepted
Commit 4598ad6a008b535d5b39e0b2727883818afbf571
Headers show
Series "RadeonSI Mega cleanup" ( rev: 1 ) in Mesa

Not browsing as part of any series.

Commit Message

Marek Olšák April 2, 2018, 4:08 a.m.
From: Marek Olšák <marek.olsak@amd.com>

---
 src/gallium/drivers/radeon/r600_cs.h              | 21 +++++----
 src/gallium/drivers/radeonsi/si_descriptors.c     | 52 +++++++++++------------
 src/gallium/drivers/radeonsi/si_state_streamout.c |  2 +-
 3 files changed, 36 insertions(+), 39 deletions(-)

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diff --git a/src/gallium/drivers/radeon/r600_cs.h b/src/gallium/drivers/radeon/r600_cs.h
index c46fad6..5cfe6ab 100644
--- a/src/gallium/drivers/radeon/r600_cs.h
+++ b/src/gallium/drivers/radeon/r600_cs.h
@@ -95,20 +95,19 @@  static inline void radeon_add_to_buffer_list(struct r600_common_context *rctx,
  *   a different constraint disallowing a context flush
  */
 static inline void
-radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
-				    struct r600_ring *ring,
-				    struct r600_resource *rbo,
-				    enum radeon_bo_usage usage,
-				    enum radeon_bo_priority priority,
-				    bool check_mem)
+radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
+					struct r600_resource *rbo,
+					enum radeon_bo_usage usage,
+					enum radeon_bo_priority priority,
+					bool check_mem)
 {
 	if (check_mem &&
-	    !radeon_cs_memory_below_limit(rctx->screen, ring->cs,
-					  rctx->vram + rbo->vram_usage,
-					  rctx->gtt + rbo->gart_usage))
-		ring->flush(rctx, PIPE_FLUSH_ASYNC, NULL);
+	    !radeon_cs_memory_below_limit(sctx->screen, sctx->b.gfx.cs,
+					  sctx->b.vram + rbo->vram_usage,
+					  sctx->b.gtt + rbo->gart_usage))
+		si_flush_gfx_cs(&sctx->b, PIPE_FLUSH_ASYNC, NULL);
 
-	radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
+	radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, rbo, usage, priority);
 }
 
 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index d0295db..e7afca2 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -265,9 +265,8 @@  static void si_sampler_view_add_buffer(struct si_context *sctx,
 	rres = (struct r600_resource*)resource;
 	priority = si_get_sampler_view_priority(rres);
 
-	radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
-					    rres, usage, priority,
-					    check_mem);
+	radeon_add_to_gfx_buffer_list_check_mem(sctx, rres, usage, priority,
+						check_mem);
 
 	if (resource->target == PIPE_BUFFER)
 		return;
@@ -275,9 +274,8 @@  static void si_sampler_view_add_buffer(struct si_context *sctx,
 	/* Now add separate DCC or HTILE. */
 	rtex = (struct r600_texture*)resource;
 	if (rtex->dcc_separate_buffer) {
-		radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
-						    rtex->dcc_separate_buffer, usage,
-						    RADEON_PRIO_DCC, check_mem);
+		radeon_add_to_gfx_buffer_list_check_mem(sctx, rtex->dcc_separate_buffer,
+							usage, RADEON_PRIO_DCC, check_mem);
 	}
 }
 
@@ -1191,10 +1189,10 @@  static void si_set_constant_buffer(struct si_context *sctx,
 			  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
 
 		buffers->buffers[slot] = buffer;
-		radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
-						    (struct r600_resource*)buffer,
-						    buffers->shader_usage_constbuf,
-						    buffers->priority_constbuf, true);
+		radeon_add_to_gfx_buffer_list_check_mem(sctx,
+							(struct r600_resource*)buffer,
+							buffers->shader_usage_constbuf,
+							buffers->priority_constbuf, true);
 		buffers->enabled_mask |= 1u << slot;
 	} else {
 		/* Clear the descriptor. */
@@ -1289,9 +1287,9 @@  static void si_set_shader_buffers(struct pipe_context *ctx,
 			  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
 
 		pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
-		radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx, buf,
-						    buffers->shader_usage,
-						    buffers->priority, true);
+		radeon_add_to_gfx_buffer_list_check_mem(sctx, buf,
+							buffers->shader_usage,
+							buffers->priority, true);
 		buf->bind_history |= PIPE_BIND_SHADER_BUFFER;
 
 		buffers->enabled_mask |= 1u << slot;
@@ -1531,9 +1529,9 @@  static void si_reset_buffer_resources(struct si_context *sctx,
 						    old_va, buf);
 			sctx->descriptors_dirty |= 1u << descriptors_idx;
 
-			radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
-							    (struct r600_resource *)buf,
-							    usage, priority, true);
+			radeon_add_to_gfx_buffer_list_check_mem(sctx,
+								(struct r600_resource *)buf,
+								usage, priority, true);
 		}
 	}
 }
@@ -1587,10 +1585,10 @@  void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf,
 						    old_va, buf);
 			sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
 
-			radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
-							    rbuffer, buffers->shader_usage,
-							    RADEON_PRIO_SHADER_RW_BUFFER,
-							    true);
+			radeon_add_to_gfx_buffer_list_check_mem(sctx,
+								rbuffer, buffers->shader_usage,
+								RADEON_PRIO_SHADER_RW_BUFFER,
+								true);
 
 			/* Update the streamout state. */
 			if (sctx->streamout.begin_emitted)
@@ -1642,7 +1640,7 @@  void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf,
 					sctx->descriptors_dirty |=
 						1u << si_sampler_and_image_descriptors_idx(shader);
 
-					radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+					radeon_add_to_gfx_buffer_list_check_mem(sctx,
 									    rbuffer, RADEON_USAGE_READ,
 									    RADEON_PRIO_SAMPLER_BUFFER,
 									    true);
@@ -1674,8 +1672,8 @@  void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf,
 					sctx->descriptors_dirty |=
 						1u << si_sampler_and_image_descriptors_idx(shader);
 
-					radeon_add_to_buffer_list_check_mem(
-						&sctx->b, &sctx->b.gfx, rbuffer,
+					radeon_add_to_gfx_buffer_list_check_mem(
+						sctx, rbuffer,
 						RADEON_USAGE_READWRITE,
 						RADEON_PRIO_SAMPLER_BUFFER, true);
 				}
@@ -1701,8 +1699,8 @@  void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf,
 				(*tex_handle)->desc_dirty = true;
 				sctx->bindless_descriptors_dirty = true;
 
-				radeon_add_to_buffer_list_check_mem(
-					&sctx->b, &sctx->b.gfx, rbuffer,
+				radeon_add_to_gfx_buffer_list_check_mem(
+					sctx, rbuffer,
 					RADEON_USAGE_READ,
 					RADEON_PRIO_SAMPLER_BUFFER, true);
 			}
@@ -1730,8 +1728,8 @@  void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf,
 				(*img_handle)->desc_dirty = true;
 				sctx->bindless_descriptors_dirty = true;
 
-				radeon_add_to_buffer_list_check_mem(
-					&sctx->b, &sctx->b.gfx, rbuffer,
+				radeon_add_to_gfx_buffer_list_check_mem(
+					sctx, rbuffer,
 					RADEON_USAGE_READWRITE,
 					RADEON_PRIO_SAMPLER_BUFFER, true);
 			}
diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c
index 3e83243..36eab20 100644
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -201,7 +201,7 @@  static void si_set_streamout_targets(struct pipe_context *ctx,
 			/* Set the resource. */
 			pipe_resource_reference(&buffers->buffers[bufidx],
 						buffer);
-			radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+			radeon_add_to_gfx_buffer_list_check_mem(sctx,
 							    (struct r600_resource*)buffer,
 							    buffers->shader_usage,
 							    RADEON_PRIO_SHADER_RW_BUFFER,