[v2] drm/i915/gvt: Add the support of HUC_STATUS2 reg emulation for Guest VGPU

Submitted by Zhao Yakui on March 28, 2018, 7:42 a.m.

Details

Message ID 1522222927-15780-1-git-send-email-yakui.zhao@intel.com
State New
Headers show
Series "drm/i915/gvt: Add the support of HUC_STATUS2 reg emulation for Guest VGPU" ( rev: 2 ) in Intel GVT devel

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Commit Message

Zhao Yakui March 28, 2018, 7:42 a.m.
From: Zhao Yakui <yakui.zhao@intel.com>

The HUC_STATUS2 reg is used to indicate whether the Huc FW is loaded. Only
when it is loaded successfully, the user-space driver on guest can use the
Huc to do the expected operation. This provides the support of HUC_STATUS2
trap for guest VGPU.

V1->V2: Follow Zhengyu's comments to add one trap handler for HUC_STATUS2
and use the USES_HUC instead of HAS_HUC_UCODE  when initializing the
HUC_STATUS2 for guest VGPU.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by  : Singh, Satyeshwar <satyeshwar.singh@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 13 +++++++++++++
 drivers/gpu/drm/i915/gvt/mmio.c     |  6 ++++++
 2 files changed, 19 insertions(+)

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diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index a33c1c3e..499460e 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1585,6 +1585,18 @@  static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
 	return 0;
 }
 
+static int gen9p_huc_mmio_read(struct intel_vgpu *vgpu,
+	unsigned int offset, void *p_data, unsigned int bytes)
+{
+	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+	mmio_hw_access_pre(dev_priv);
+	vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
+	mmio_hw_access_post(dev_priv);
+	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
+}
+
+
 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
 	ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \
 		f, s, am, rm, d, r, w); \
@@ -2867,6 +2879,7 @@  static int init_skl_mmio_info(struct intel_gvt *gvt)
 	MMIO_D(_MMIO(0x4ab8), D_KBL);
 	MMIO_D(_MMIO(0x2248), D_SKL_PLUS | D_KBL);
 
+	MMIO_DH(HUC_STATUS2, D_GEN9PLUS, gen9p_huc_mmio_read, NULL);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 11b71b3..a71cf06 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -235,6 +235,7 @@  void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
 	struct intel_gvt *gvt = vgpu->gvt;
 	const struct intel_gvt_device_info *info = &gvt->device_info;
 	void  *mmio = gvt->firmware.mmio;
+	struct drm_i915_private *dev_priv = gvt->dev_priv;
 
 	if (dmlr) {
 		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
@@ -256,6 +257,11 @@  void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
 		memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
 	}
 
+	if (USES_HUC(dev_priv)) {
+		mmio_hw_access_pre(dev_priv);
+		vgpu_vreg_t(vgpu, HUC_STATUS2) = I915_READ(HUC_STATUS2);
+		mmio_hw_access_post(dev_priv);
+	}
 }
 
 /**