[08/14] drm/i915/gvt: Make PTE iterator 64K entry aware

Submitted by changbin.du@intel.com on March 15, 2018, 7:05 a.m.

Details

Message ID 1521097513-7183-9-git-send-email-changbin.du@intel.com
State New
Headers show
Series "drm/i915/gvt: Add huge gtt shadowing" ( rev: 1 ) in Intel GVT devel

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Commit Message

changbin.du@intel.com March 15, 2018, 7:05 a.m.
From: Changbin Du <changbin.du@intel.com>

64K PTE is special, only PTE#0, PTE#16, PTE#32, ... PTE#496 are used in
the page table.

Signed-off-by: Changbin Du <changbin.du@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

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diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 75b4db9..185726d 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -348,6 +348,8 @@  static inline int gtt_set_entry64(void *pt,
 #define ADDR_64K_MASK	GENMASK_ULL(GTT_HAW - 1, 16)
 #define ADDR_4K_MASK	GENMASK_ULL(GTT_HAW - 1, 12)
 
+#define GTT_64K_PTE_STRIDE 16
+
 #define GTT_SPTE_FLAG_MASK GENMASK(52, 62)
 #define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
 
@@ -879,12 +881,14 @@  static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt_gfn(
 	(I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
 
 #define for_each_present_guest_entry(spt, e, i) \
-	for (i = 0; i < pt_entries(spt); i++) \
+	for (i = 0; i < pt_entries(spt); \
+	     i += spt->guest_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
 		if (!ppgtt_get_guest_entry(spt, e, i) && \
 		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
 
 #define for_each_present_shadow_entry(spt, e, i) \
-	for (i = 0; i < pt_entries(spt); i++) \
+	for (i = 0; i < pt_entries(spt); \
+	     i += spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
 		if (!ppgtt_get_shadow_entry(spt, e, i) && \
 		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))