[06/14] drm/i915/gvt: Add GTT clear_pse operation

Submitted by changbin.du@intel.com on March 15, 2018, 7:05 a.m.

Details

Message ID 1521097513-7183-7-git-send-email-changbin.du@intel.com
State New
Headers show
Series "drm/i915/gvt: Add huge gtt shadowing" ( rev: 1 ) in Intel GVT devel

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Commit Message

changbin.du@intel.com March 15, 2018, 7:05 a.m.
From: Changbin Du <changbin.du@intel.com>

If we cannot setup 2M gtt page, we need split it into small pages.

Signed-off-by: Changbin Du <changbin.du@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h |  1 +
 2 files changed, 20 insertions(+)

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diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 05b724e..05f9bb6 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -390,6 +390,24 @@  static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
 	return !!(e->val64 & _PAGE_PSE);
 }
 
+static void gen8_gtt_clear_pse(struct intel_gvt_gtt_entry *e)
+{
+	if (gen8_gtt_test_pse(e)) {
+		switch (e->type) {
+		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
+			e->val64 &= ~_PAGE_PSE;
+			e->type = GTT_TYPE_PPGTT_PDE_ENTRY;
+			break;
+		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
+			e->type = GTT_TYPE_PPGTT_PDP_ENTRY;
+			e->val64 &= ~_PAGE_PSE;
+			break;
+		default:
+			WARN_ON(1);
+		}
+	}
+}
+
 static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
 {
 	if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
@@ -477,6 +495,7 @@  static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
 	.set_present = gtt_entry_set_present,
 	.test_present = gen8_gtt_test_present,
 	.test_pse = gen8_gtt_test_pse,
+	.clear_pse = gen8_gtt_clear_pse,
 	.clear_ips = gen8_gtt_clear_ips,
 	.test_ips = gen8_gtt_test_ips,
 	.clear_64k_splited = gen8_gtt_clear_64k_splited,
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 0122185..62f65b5 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -63,6 +63,7 @@  struct intel_gvt_gtt_pte_ops {
 	void (*clear_present)(struct intel_gvt_gtt_entry *e);
 	void (*set_present)(struct intel_gvt_gtt_entry *e);
 	bool (*test_pse)(struct intel_gvt_gtt_entry *e);
+	void (*clear_pse)(struct intel_gvt_gtt_entry *e);
 	bool (*test_ips)(struct intel_gvt_gtt_entry *e);
 	void (*clear_ips)(struct intel_gvt_gtt_entry *e);
 	bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e);

Comments

On 2018.03.15 15:05:05 +0800, changbin.du@intel.com wrote:
> From: Changbin Du <changbin.du@intel.com>
> 
> If we cannot setup 2M gtt page, we need split it into small pages.
>

Looks commit description doesn't match title and patch content.

> Signed-off-by: Changbin Du <changbin.du@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/gtt.c | 19 +++++++++++++++++++
>  drivers/gpu/drm/i915/gvt/gtt.h |  1 +
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 05b724e..05f9bb6 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -390,6 +390,24 @@ static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
>  	return !!(e->val64 & _PAGE_PSE);
>  }
>  
> +static void gen8_gtt_clear_pse(struct intel_gvt_gtt_entry *e)
> +{
> +	if (gen8_gtt_test_pse(e)) {
> +		switch (e->type) {
> +		case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
> +			e->val64 &= ~_PAGE_PSE;
> +			e->type = GTT_TYPE_PPGTT_PDE_ENTRY;
> +			break;
> +		case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
> +			e->type = GTT_TYPE_PPGTT_PDP_ENTRY;
> +			e->val64 &= ~_PAGE_PSE;
> +			break;
> +		default:
> +			WARN_ON(1);
> +		}
> +	}
> +}
> +
>  static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
>  {
>  	if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
> @@ -477,6 +495,7 @@ static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
>  	.set_present = gtt_entry_set_present,
>  	.test_present = gen8_gtt_test_present,
>  	.test_pse = gen8_gtt_test_pse,
> +	.clear_pse = gen8_gtt_clear_pse,
>  	.clear_ips = gen8_gtt_clear_ips,
>  	.test_ips = gen8_gtt_test_ips,
>  	.clear_64k_splited = gen8_gtt_clear_64k_splited,
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
> index 0122185..62f65b5 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.h
> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> @@ -63,6 +63,7 @@ struct intel_gvt_gtt_pte_ops {
>  	void (*clear_present)(struct intel_gvt_gtt_entry *e);
>  	void (*set_present)(struct intel_gvt_gtt_entry *e);
>  	bool (*test_pse)(struct intel_gvt_gtt_entry *e);
> +	void (*clear_pse)(struct intel_gvt_gtt_entry *e);
>  	bool (*test_ips)(struct intel_gvt_gtt_entry *e);
>  	void (*clear_ips)(struct intel_gvt_gtt_entry *e);
>  	bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e);
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
On Fri, Mar 23, 2018 at 11:22:18AM +0800, Zhenyu Wang wrote:
> On 2018.03.15 15:05:05 +0800, changbin.du@intel.com wrote:
> > From: Changbin Du <changbin.du@intel.com>
> > 
> > If we cannot setup 2M gtt page, we need split it into small pages.
> >
> 
> Looks commit description doesn't match title and patch content.
> 

oops...