[05/14] drm/i915/gvt: Add software PTE flag to mark special 64K splited entry

Submitted by changbin.du@intel.com on March 15, 2018, 7:05 a.m.

Details

Message ID 1521097513-7183-6-git-send-email-changbin.du@intel.com
State New
Headers show
Series "drm/i915/gvt: Add huge gtt shadowing" ( rev: 1 ) in Intel GVT devel

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Commit Message

changbin.du@intel.com March 15, 2018, 7:05 a.m.
From: Changbin Du <changbin.du@intel.com>

This add a software PTE flag on the Ignored bit of PTE. It will be used
to identify splited 64K shadow entries.

Signed-off-by: Changbin Du <changbin.du@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h |  3 +++
 2 files changed, 24 insertions(+)

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diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 2bc7afd..05b724e 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -348,6 +348,9 @@  static inline int gtt_set_entry64(void *pt,
 #define ADDR_64K_MASK	GENMASK_ULL(GTT_HAW - 1, 16)
 #define ADDR_4K_MASK	GENMASK_ULL(GTT_HAW - 1, 12)
 
+#define GTT_SPTE_FLAG_MASK GENMASK(52, 62)
+#define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
+
 static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
 {
 	unsigned long pfn;
@@ -427,6 +430,21 @@  static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
 	e->val64 |= _PAGE_PRESENT;
 }
 
+static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
+{
+	return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
+}
+
+static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
+{
+	e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
+}
+
+static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
+{
+	e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
+}
+
 /*
  * Per-platform GMA routines.
  */
@@ -461,6 +479,9 @@  static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
 	.test_pse = gen8_gtt_test_pse,
 	.clear_ips = gen8_gtt_clear_ips,
 	.test_ips = gen8_gtt_test_ips,
+	.clear_64k_splited = gen8_gtt_clear_64k_splited,
+	.set_64k_splited = gen8_gtt_set_64k_splited,
+	.test_64k_splited = gen8_gtt_test_64k_splited,
 	.get_pfn = gen8_gtt_get_pfn,
 	.set_pfn = gen8_gtt_set_pfn,
 };
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index 93b3018..0122185 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -65,6 +65,9 @@  struct intel_gvt_gtt_pte_ops {
 	bool (*test_pse)(struct intel_gvt_gtt_entry *e);
 	bool (*test_ips)(struct intel_gvt_gtt_entry *e);
 	void (*clear_ips)(struct intel_gvt_gtt_entry *e);
+	bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e);
+	void (*clear_64k_splited)(struct intel_gvt_gtt_entry *e);
+	void (*set_64k_splited)(struct intel_gvt_gtt_entry *e);
 	void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn);
 	unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e);
 };

Comments

On 2018.03.15 15:05:04 +0800, changbin.du@intel.com wrote:
> From: Changbin Du <changbin.du@intel.com>
> 
> This add a software PTE flag on the Ignored bit of PTE. It will be used
> to identify splited 64K shadow entries.
> 
> Signed-off-by: Changbin Du <changbin.du@intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/gtt.c | 21 +++++++++++++++++++++
>  drivers/gpu/drm/i915/gvt/gtt.h |  3 +++
>  2 files changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 2bc7afd..05b724e 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -348,6 +348,9 @@ static inline int gtt_set_entry64(void *pt,
>  #define ADDR_64K_MASK	GENMASK_ULL(GTT_HAW - 1, 16)
>  #define ADDR_4K_MASK	GENMASK_ULL(GTT_HAW - 1, 12)
>  
> +#define GTT_SPTE_FLAG_MASK GENMASK(52, 62)

GENMASK low to high?

> +#define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
> +
>  static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
>  {
>  	unsigned long pfn;
> @@ -427,6 +430,21 @@ static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
>  	e->val64 |= _PAGE_PRESENT;
>  }
>  
> +static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
> +{
> +	return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
> +}
> +
> +static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
> +{
> +	e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
> +}
> +
> +static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
> +{
> +	e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
> +}
> +
>  /*
>   * Per-platform GMA routines.
>   */
> @@ -461,6 +479,9 @@ static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
>  	.test_pse = gen8_gtt_test_pse,
>  	.clear_ips = gen8_gtt_clear_ips,
>  	.test_ips = gen8_gtt_test_ips,
> +	.clear_64k_splited = gen8_gtt_clear_64k_splited,
> +	.set_64k_splited = gen8_gtt_set_64k_splited,
> +	.test_64k_splited = gen8_gtt_test_64k_splited,
>  	.get_pfn = gen8_gtt_get_pfn,
>  	.set_pfn = gen8_gtt_set_pfn,
>  };
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
> index 93b3018..0122185 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.h
> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> @@ -65,6 +65,9 @@ struct intel_gvt_gtt_pte_ops {
>  	bool (*test_pse)(struct intel_gvt_gtt_entry *e);
>  	bool (*test_ips)(struct intel_gvt_gtt_entry *e);
>  	void (*clear_ips)(struct intel_gvt_gtt_entry *e);
> +	bool (*test_64k_splited)(struct intel_gvt_gtt_entry *e);
> +	void (*clear_64k_splited)(struct intel_gvt_gtt_entry *e);
> +	void (*set_64k_splited)(struct intel_gvt_gtt_entry *e);
>  	void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn);
>  	unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e);
>  };
> -- 
> 2.7.4
> 
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev
On Fri, Mar 23, 2018 at 11:20:42AM +0800, Zhenyu Wang wrote:
> On 2018.03.15 15:05:04 +0800, changbin.du@intel.com wrote:
> > From: Changbin Du <changbin.du@intel.com>
> > 
> > This add a software PTE flag on the Ignored bit of PTE. It will be used
> > to identify splited 64K shadow entries.
> > 
> > Signed-off-by: Changbin Du <changbin.du@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gvt/gtt.c | 21 +++++++++++++++++++++
> >  drivers/gpu/drm/i915/gvt/gtt.h |  3 +++
> >  2 files changed, 24 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> > index 2bc7afd..05b724e 100644
> > --- a/drivers/gpu/drm/i915/gvt/gtt.c
> > +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> > @@ -348,6 +348,9 @@ static inline int gtt_set_entry64(void *pt,
> >  #define ADDR_64K_MASK	GENMASK_ULL(GTT_HAW - 1, 16)
> >  #define ADDR_4K_MASK	GENMASK_ULL(GTT_HAW - 1, 12)
> >  
> > +#define GTT_SPTE_FLAG_MASK GENMASK(52, 62)
> 
> GENMASK low to high?
> 

Yes, thanks for pointing out!