drm/amdgpu: Clean sdma wptr register when only enable wptr polling

Submitted by Deng, Emily on March 6, 2018, 9:17 a.m.

Details

Message ID 1520327844-23228-1-git-send-email-Emily.Deng@amd.com
State New
Headers show
Series "drm/amdgpu: Clean sdma wptr register when only enable wptr polling" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Deng, Emily March 6, 2018, 9:17 a.m.
The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 521978c..2a27928 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -719,11 +719,12 @@  static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
 		       upper_32_bits(wptr_gpu_addr));
 		wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
-		if (ring->use_pollmem)
+		if (ring->use_pollmem) {
+			WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 						       SDMA0_GFX_RB_WPTR_POLL_CNTL,
 						       ENABLE, 1);
-		else
+		} else
 			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 						       SDMA0_GFX_RB_WPTR_POLL_CNTL,
 						       ENABLE, 0);

Comments

Better to add comment above the code.

Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>



> -----Original Message-----

> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf

> Of Emily Deng

> Sent: Tuesday, March 06, 2018 5:17 PM

> To: amd-gfx@lists.freedesktop.org

> Cc: Deng, Emily <Emily.Deng@amd.com>

> Subject: [PATCH] drm/amdgpu: Clean sdma wptr register when only enable

> wptr polling

> 

> The sdma wptr polling memory is not fast enough, then the sdma wptr

> register will be random, and not equal to sdma rptr, which will cause sdma

> engine hang when load driver, so clean up the sdma wptr directly to fix this

> issue.

> 

> Signed-off-by: Emily Deng <Emily.Deng@amd.com>

> ---

>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++--

>  1 file changed, 3 insertions(+), 2 deletions(-)

> 

> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

> index 521978c..2a27928 100644

> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

> @@ -719,11 +719,12 @@ static int sdma_v3_0_gfx_resume(struct

> amdgpu_device *adev)

>  		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI +

> sdma_offsets[i],

>  		       upper_32_bits(wptr_gpu_addr));

>  		wptr_poll_cntl =

> RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);

> -		if (ring->use_pollmem)

> +		if (ring->use_pollmem) {

> +			WREG32(mmSDMA0_GFX_RB_WPTR +

> sdma_offsets[i], 0);

>  			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

> 

> SDMA0_GFX_RB_WPTR_POLL_CNTL,

>  						       ENABLE, 1);

> -		else

> +		} else

>  			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

> 

> SDMA0_GFX_RB_WPTR_POLL_CNTL,

>  						       ENABLE, 0);

> --

> 2.7.4

> 

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