drm/amdgpu: Disable sdma wptr polling memory for sriov

Submitted by Deng, Emily on March 6, 2018, 2:14 a.m.

Details

Message ID 1520302493-20759-1-git-send-email-Emily.Deng@amd.com
State New
Headers show
Series "drm/amdgpu: Disable sdma wptr polling memory for sriov" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Deng, Emily March 6, 2018, 2:14 a.m.
The sdma wptr polling memory will introduce serious issue sdma hang for
sriov environment on sdma v3.
And the sdma wptr polling memory is only to fix the FLR cornner case, the
issue's probabity is very low.

Change-Id: I2c447533aac6b16d541f58644d141228dd75dfb3
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index ec885ff..44d7d08 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -716,10 +716,7 @@  static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
 		       upper_32_bits(wptr_gpu_addr));
 		wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
-		if (amdgpu_sriov_vf(adev))
-			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
-		else
-			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
+		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
 		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
 
 		/* enable DMA RB */

Comments

Hi all,
     Please ignore this patch, the root cause about the sdma hang introduced by sdma wptr polling
has been found, will submit another patch.

Best Wishes,
Emily Deng

> -----Original Message-----
> From: Emily Deng [mailto:Emily.Deng@amd.com]
> Sent: Tuesday, March 06, 2018 10:15 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily <Emily.Deng@amd.com>
> Subject: [PATCH] drm/amdgpu: Disable sdma wptr polling memory for sriov
> 
> The sdma wptr polling memory will introduce serious issue sdma hang for
> sriov environment on sdma v3.
> And the sdma wptr polling memory is only to fix the FLR cornner case, the
> issue's probabity is very low.
> 
> Change-Id: I2c447533aac6b16d541f58644d141228dd75dfb3
> Signed-off-by: Emily Deng <Emily.Deng@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +----
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index ec885ff..44d7d08 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -716,10 +716,7 @@ static int sdma_v3_0_gfx_resume(struct
> amdgpu_device *adev)
>  		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI +
> sdma_offsets[i],
>  		       upper_32_bits(wptr_gpu_addr));
>  		wptr_poll_cntl =
> RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
> -		if (amdgpu_sriov_vf(adev))
> -			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
> -		else
> -			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
> +		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
> +SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
>  		WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL +
> sdma_offsets[i], wptr_poll_cntl);
> 
>  		/* enable DMA RB */
> --
> 2.7.4