rnndb/adreno: Add more PM4 opcodes

Submitted by Sharat Masetty on March 2, 2018, 8:09 a.m.

Details

Message ID 1519978187-1573-1-git-send-email-smasetty@codeaurora.org
State New
Headers show
Series "rnndb/adreno: Add more PM4 opcodes" ( rev: 1 ) in DRI devel

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Commit Message

Sharat Masetty March 2, 2018, 8:09 a.m.
Add CP_SECURE_MODE and CP_SET_PSEUDO_REG opcodes needed for A6xx
hardware features.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
 rnndb/adreno/adreno_pm4.xml | 5 +++++
 1 file changed, 5 insertions(+)

--
1.9.1

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diff --git a/rnndb/adreno/adreno_pm4.xml b/rnndb/adreno/adreno_pm4.xml
index 3621f07..c1a82da 100644
--- a/rnndb/adreno/adreno_pm4.xml
+++ b/rnndb/adreno/adreno_pm4.xml
@@ -288,6 +288,11 @@  xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 	<!-- switches SMMU pagetable, used on a5xx only -->
 	<value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
 	<value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX"/>
+	<!-- for a6xx -->
+	<doc>Tells CP the current mode of GPU operation</doc>
+	<value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
+	<doc>Instruct CP to set a few inernal CP registers</doc>
+	<value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
 	<!--
 	pairs of regid and value.. seems to be used to program some TF
 	related regs: