[Mesa-dev,2/3] i965: replace hiz_mt by hiz_region

Submitted by Chia-I Wu on Feb. 18, 2014, 8:44 a.m.

Details

Message ID 1392713085-4173-2-git-send-email-olvaffe@gmail.com
State New
Headers show

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Commit Message

Chia-I Wu Feb. 18, 2014, 8:44 a.m.
HiZ buffers are opaque to the driver, and keeping the miptree around does not
gain us anything.

Signed-off-by: Chia-I Wu <olv@lunarg.com>
---
 src/mesa/drivers/dri/i965/brw_misc_state.c    |  9 ++++-----
 src/mesa/drivers/dri/i965/gen6_blorp.cpp      |  2 +-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp      |  2 +-
 src/mesa/drivers/dri/i965/gen7_misc_state.c   |  5 ++---
 src/mesa/drivers/dri/i965/intel_fbo.c         |  4 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 ++++++++++++-----
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 18 ++++++++----------
 7 files changed, 30 insertions(+), 27 deletions(-)

Patch hide | download patch | download mbox

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 4e95c27..c3d3ad3 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -215,7 +215,7 @@  brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
 
       if (intel_miptree_slice_has_hiz(depth_mt, depth_level, depth_layer)) {
          uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
-         intel_region_get_tile_masks(depth_mt->hiz_mt->region,
+         intel_region_get_tile_masks(depth_mt->hiz_region,
                                      &hiz_tile_mask_x, &hiz_tile_mask_y, false);
 
          /* Each HiZ row represents 2 rows of pixels */
@@ -483,7 +483,7 @@  brw_workaround_depthstencil_alignment(struct brw_context *brw,
                                          false);
       if (intel_renderbuffer_has_hiz(depth_irb)) {
          brw->depthstencil.hiz_offset =
-            intel_region_get_aligned_offset(depth_mt->hiz_mt->region,
+            intel_region_get_aligned_offset(depth_mt->hiz_region,
                                             depth_irb->draw_x & ~tile_mask_x,
                                             (depth_irb->draw_y & ~tile_mask_y) /
                                             2,
@@ -671,11 +671,10 @@  brw_emit_depth_stencil_hiz(struct brw_context *brw,
 
       /* Emit hiz buffer. */
       if (hiz) {
-         struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
 	 BEGIN_BATCH(3);
 	 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-	 OUT_BATCH(hiz_mt->region->pitch - 1);
-	 OUT_RELOC(hiz_mt->region->bo,
+	 OUT_BATCH(depth_mt->hiz_region->pitch - 1);
+	 OUT_RELOC(depth_mt->hiz_region->bo,
 		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		   brw->depthstencil.hiz_offset);
 	 ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 4222fa8..8cc2df1 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -856,7 +856,7 @@  gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_HIER_DEPTH_BUFFER */
    {
-      struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
+      struct intel_region *hiz_region = params->depth.mt->hiz_region;
       uint32_t hiz_offset =
          intel_region_get_aligned_offset(hiz_region,
                                          draw_x & ~tile_mask_x,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 4bf9396..b1c4461 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -753,7 +753,7 @@  gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_HIER_DEPTH_BUFFER */
    {
-      struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
+      struct intel_region *hiz_region = params->depth.mt->hiz_region;
 
       BEGIN_BATCH(3);
       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 8fb0eec..0fa0ed6 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -143,12 +143,11 @@  gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
-      struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
       OUT_BATCH((mocs << 25) |
-                (hiz_mt->region->pitch - 1));
-      OUT_RELOC(hiz_mt->region->bo,
+                (depth_mt->hiz_region->pitch - 1));
+      OUT_RELOC(depth_mt->hiz_region->bo,
                 I915_GEM_DOMAIN_RENDER,
                 I915_GEM_DOMAIN_RENDER,
                 0);
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index cd148f0..61c570a 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -442,9 +442,9 @@  intel_renderbuffer_update_wrapper(struct brw_context *brw,
 
    intel_renderbuffer_set_draw_offset(irb);
 
-   if (mt->hiz_mt == NULL && brw_is_hiz_depth_format(brw, rb->Format)) {
+   if (mt->hiz_region == NULL && brw_is_hiz_depth_format(brw, rb->Format)) {
       intel_miptree_alloc_hiz(brw, mt);
-      if (!mt->hiz_mt)
+      if (!mt->hiz_region)
 	 return false;
    }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c9f5bb3..c40503a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -864,8 +864,8 @@  intel_miptree_release(struct intel_mipmap_tree **mt)
       DBG("%s deleting %p\n", __FUNCTION__, *mt);
 
       intel_region_release(&((*mt)->region));
+      intel_region_release(&(*mt)->hiz_region);
       intel_miptree_release(&(*mt)->stencil_mt);
-      intel_miptree_release(&(*mt)->hiz_mt);
       intel_miptree_release(&(*mt)->mcs_mt);
       intel_miptree_release(&(*mt)->singlesample_mt);
       intel_resolve_map_clear(&(*mt)->hiz_map);
@@ -1322,7 +1322,7 @@  intel_miptree_slice_enable_hiz(struct brw_context *brw,
                                uint32_t level,
                                uint32_t layer)
 {
-   assert(mt->hiz_mt);
+   assert(mt->hiz_region);
 
    if (brw->is_haswell) {
       const struct intel_mipmap_level *l = &mt->level[level];
@@ -1348,8 +1348,11 @@  bool
 intel_miptree_alloc_hiz(struct brw_context *brw,
 			struct intel_mipmap_tree *mt)
 {
-   assert(mt->hiz_mt == NULL);
-   mt->hiz_mt = intel_miptree_create(brw,
+   struct intel_mipmap_tree *tmp_hiz_mt;
+
+   assert(mt->hiz_region == NULL);
+
+   tmp_hiz_mt = intel_miptree_create(brw,
                                      mt->target,
                                      mt->format,
                                      mt->first_level,
@@ -1360,8 +1363,12 @@  intel_miptree_alloc_hiz(struct brw_context *brw,
                                      true,
                                      mt->num_samples,
                                      INTEL_MIPTREE_TILING_ANY);
+   if (tmp_hiz_mt) {
+      intel_region_reference(&mt->hiz_region, tmp_hiz_mt->region);
+      intel_miptree_release(&tmp_hiz_mt);
+   }
 
-   if (!mt->hiz_mt)
+   if (!mt->hiz_region)
       return false;
 
    /* Mark that all slices need a HiZ resolve. */
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 0c0a3d3..9e9d8c6 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -157,9 +157,8 @@  struct intel_mipmap_level
       /**
        * \brief Is HiZ enabled for this slice?
        *
-       * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt
-       * has been allocated and (2) the HiZ memory corresponding to this slice
-       * resides at \c mt->hiz_mt->level[l].slice[s].
+       * If \c mt->level[l].slice[s].has_hiz is set, then \c mt->hiz_region
+       * has been allocated.
        */
       bool has_hiz;
    } *slice;
@@ -413,15 +412,15 @@  struct intel_mipmap_tree
    bool need_downsample;
 
    /**
-    * \brief HiZ miptree
+    * \brief HiZ buffer
     *
-    * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
-    * miptree, use intel_miptree_alloc_hiz().
+    * The hiz region contains the miptree's hiz buffer. To allocate the hiz
+    * region, use intel_miptree_alloc_hiz().
     *
     * To determine if hiz is enabled, do not check this pointer. Instead, use
     * intel_miptree_slice_has_hiz().
     */
-   struct intel_mipmap_tree *hiz_mt;
+   struct intel_region *hiz_region;
 
    /**
     * \brief Map of miptree slices to needed resolves.
@@ -429,8 +428,7 @@  struct intel_mipmap_tree
     * This is used only when the miptree has a child HiZ miptree.
     *
     * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is
-    * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c
-    * mt->hiz_mt->hiz_map, is unused.
+    * \c mt->hiz_map.
     */
    struct intel_resolve_map hiz_map;
 
@@ -622,7 +620,7 @@  intel_miptree_alloc_mcs(struct brw_context *brw,
 
 /**
  * \brief Allocate the miptree's embedded HiZ miptree.
- * \see intel_mipmap_tree:hiz_mt
+ * \see intel_mipmap_tree:hiz_region
  * \return false if allocation failed
  */