[1/8] amd/common:add uvd hevc enc support check in hw query

Submitted by Zhu, James on Feb. 5, 2018, 5:16 p.m.

Details

Message ID 1517850967-29087-1-git-send-email-James.Zhu@amd.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Mesa

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Commit Message

Zhu, James Feb. 5, 2018, 5:16 p.m.
Based on amdgpu hardware query information to check if UVD hevc enc support

Signed-off-by: James Zhu <James.Zhu@amd.com>
---
 src/amd/common/ac_gpu_info.c | 10 +++++++++-
 src/amd/common/ac_gpu_info.h |  1 +
 2 files changed, 10 insertions(+), 1 deletion(-)

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diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6d9dcb5..2494967 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -98,7 +98,7 @@  bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 {
 	struct amdgpu_buffer_size_alignments alignment_info = {};
 	struct amdgpu_heap_info vram, vram_vis, gtt;
-	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
+	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
 	uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
 	int r, i, j;
 	drmDevicePtr devinfo;
@@ -166,6 +166,12 @@  bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		return false;
 	}
 
+	r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
+	if (r) {
+		fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
+		return false;
+	}
+
 	if (info->drm_major == 3 && info->drm_minor >= 17) {
 		r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
 		if (r) {
@@ -275,6 +281,8 @@  bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 		uvd.available_rings ? uvd_version : 0;
 	info->vce_fw_version =
 		vce.available_rings ? vce_version : 0;
+	info->uvd_enc_supported =
+		uvd_enc.available_rings ? true : false;
 	info->has_userptr = true;
 	info->has_syncobj = has_syncobj(fd);
 	info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index cca3e98..6b120d1 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -65,6 +65,7 @@  struct radeon_info {
 	uint32_t                    num_compute_rings;
 	uint32_t                    uvd_fw_version;
 	uint32_t                    vce_fw_version;
+	bool						uvd_enc_supported;
 	uint32_t                    me_fw_version;
 	uint32_t                    me_fw_feature;
 	uint32_t                    pfp_fw_version;

Comments

On 2018-02-05 12:16 PM, James Zhu wrote:
> Based on amdgpu hardware query information to check if UVD hevc enc support
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
>   src/amd/common/ac_gpu_info.c | 10 +++++++++-
>   src/amd/common/ac_gpu_info.h |  1 +
>   2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index 6d9dcb5..2494967 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -98,7 +98,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>   {
>   	struct amdgpu_buffer_size_alignments alignment_info = {};
>   	struct amdgpu_heap_info vram, vram_vis, gtt;
> -	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
> +	struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
>   	uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
>   	int r, i, j;
>   	drmDevicePtr devinfo;
> @@ -166,6 +166,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>   		return false;
>   	}
>   
> +	r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
> +	if (r) {
> +		fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
> +		return false;
> +	}
> +
>   	if (info->drm_major == 3 && info->drm_minor >= 17) {
>   		r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
>   		if (r) {
> @@ -275,6 +281,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>   		uvd.available_rings ? uvd_version : 0;
>   	info->vce_fw_version =
>   		vce.available_rings ? vce_version : 0;
> +	info->uvd_enc_supported =
> +		uvd_enc.available_rings ? true : false;
>   	info->has_userptr = true;
>   	info->has_syncobj = has_syncobj(fd);
>   	info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index cca3e98..6b120d1 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -65,6 +65,7 @@ struct radeon_info {
>   	uint32_t                    num_compute_rings;
>   	uint32_t                    uvd_fw_version;
>   	uint32_t                    vce_fw_version;
> +	bool						uvd_enc_supported;

White space/tab length seems not correct here. With that fixed, this 
patch is
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>

Thanks,
Boyuan

>   	uint32_t                    me_fw_version;
>   	uint32_t                    me_fw_feature;
>   	uint32_t                    pfp_fw_version;