[4/8] intel/blorp: Add suport for fast clear address.

Submitted by Rafael Antognolli on Dec. 15, 2017, 10:53 p.m.

Details

Message ID 20171215225335.28009-4-rafael.antognolli@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Mesa

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Commit Message

Rafael Antognolli Dec. 15, 2017, 10:53 p.m.
On gen10+, if surface->clear_color_addr is present, use it directly
intead of copying it to the surface state.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
---
 src/intel/blorp/blorp_genX_exec.h | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

Patch hide | download patch | download mbox

diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 1968460be05..a01d21c2cdd 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1276,11 +1276,15 @@  blorp_emit_surface_state(struct blorp_batch *batch,
          write_disable_mask |= ISL_CHANNEL_ALPHA_BIT;
    }
 
+   const bool use_clear_address =
+      GEN_GEN >= 10 && (surface->clear_color_addr.buffer != NULL);
+
    isl_surf_fill_state(batch->blorp->isl_dev, state,
                        .surf = &surf, .view = &surface->view,
                        .aux_surf = &surface->aux_surf, .aux_usage = aux_usage,
                        .mocs = surface->addr.mocs,
                        .clear_color = surface->clear_color,
+                       .use_clear_address = use_clear_address,
                        .write_disables = write_disable_mask);
 
    blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
@@ -1300,9 +1304,11 @@  blorp_emit_surface_state(struct blorp_batch *batch,
    blorp_flush_range(batch, state, GENX(RENDER_SURFACE_STATE_length) * 4);
 
    if (surface->clear_color_addr.buffer) {
-#if GEN_GEN > 10
-      unreachable("Implement indirect clear support on gen11+");
-#elif GEN_GEN >= 7 && GEN_GEN <= 10
+#if GEN_GEN >= 10
+      assert((surface->clear_color_addr.offset & 0x3f) == 0);
+      blorp_surface_reloc(batch, state_offset + isl_dev->ss.clear_value_offset,
+                          surface->clear_color_addr, 0);
+#elif GEN_GEN >= 7 && GEN_GEN < 10
       struct blorp_address dst_addr = blorp_get_surface_base_address(batch);
       dst_addr.offset += state_offset + isl_dev->ss.clear_value_offset;
       blorp_emit_memcpy(batch, dst_addr, surface->clear_color_addr,

Comments

On Fri, Dec 15, 2017 at 2:53 PM, Rafael Antognolli <
rafael.antognolli@intel.com> wrote:

> On gen10+, if surface->clear_color_addr is present, use it directly
> intead of copying it to the surface state.
>
> Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
> ---
>  src/intel/blorp/blorp_genX_exec.h | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/src/intel/blorp/blorp_genX_exec.h
> b/src/intel/blorp/blorp_genX_exec.h
> index 1968460be05..a01d21c2cdd 100644
> --- a/src/intel/blorp/blorp_genX_exec.h
> +++ b/src/intel/blorp/blorp_genX_exec.h
> @@ -1276,11 +1276,15 @@ blorp_emit_surface_state(struct blorp_batch
> *batch,
>           write_disable_mask |= ISL_CHANNEL_ALPHA_BIT;
>     }
>
> +   const bool use_clear_address =
> +      GEN_GEN >= 10 && (surface->clear_color_addr.buffer != NULL);
> +
>     isl_surf_fill_state(batch->blorp->isl_dev, state,
>                         .surf = &surf, .view = &surface->view,
>                         .aux_surf = &surface->aux_surf, .aux_usage =
> aux_usage,
>                         .mocs = surface->addr.mocs,
>                         .clear_color = surface->clear_color,
> +                       .use_clear_address = use_clear_address,
>                         .write_disables = write_disable_mask);
>
>     blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
> @@ -1300,9 +1304,11 @@ blorp_emit_surface_state(struct blorp_batch *batch,
>     blorp_flush_range(batch, state, GENX(RENDER_SURFACE_STATE_length) *
> 4);
>
>     if (surface->clear_color_addr.buffer) {
> -#if GEN_GEN > 10
> -      unreachable("Implement indirect clear support on gen11+");
> -#elif GEN_GEN >= 7 && GEN_GEN <= 10
> +#if GEN_GEN >= 10
> +      assert((surface->clear_color_addr.offset & 0x3f) == 0);
> +      blorp_surface_reloc(batch, state_offset + isl_dev->ss.clear_value_
> offset,
>

Are the value offset and the address offset the same?  I think they are,
but just want to be sure. :-)


> +                          surface->clear_color_addr, 0);
> +#elif GEN_GEN >= 7 && GEN_GEN < 10
>        struct blorp_address dst_addr = blorp_get_surface_base_
> address(batch);
>        dst_addr.offset += state_offset + isl_dev->ss.clear_value_offset;
>        blorp_emit_memcpy(batch, dst_addr, surface->clear_color_addr,
> --
> 2.14.3
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
On Mon, Jan 08, 2018 at 04:06:53PM -0800, Jason Ekstrand wrote:
> On Fri, Dec 15, 2017 at 2:53 PM, Rafael Antognolli <rafael.antognolli@intel.com
> > wrote:
> 
>     On gen10+, if surface->clear_color_addr is present, use it directly
>     intead of copying it to the surface state.
> 
>     Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
>     ---
>      src/intel/blorp/blorp_genX_exec.h | 12 +++++++++---
>      1 file changed, 9 insertions(+), 3 deletions(-)
> 
>     diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/
>     blorp_genX_exec.h
>     index 1968460be05..a01d21c2cdd 100644
>     --- a/src/intel/blorp/blorp_genX_exec.h
>     +++ b/src/intel/blorp/blorp_genX_exec.h
>     @@ -1276,11 +1276,15 @@ blorp_emit_surface_state(struct blorp_batch *batch,
>               write_disable_mask |= ISL_CHANNEL_ALPHA_BIT;
>         }
> 
>     +   const bool use_clear_address =
>     +      GEN_GEN >= 10 && (surface->clear_color_addr.buffer != NULL);
>     +
>         isl_surf_fill_state(batch->blorp->isl_dev, state,
>                             .surf = &surf, .view = &surface->view,
>                             .aux_surf = &surface->aux_surf, .aux_usage =
>     aux_usage,
>                             .mocs = surface->addr.mocs,
>                             .clear_color = surface->clear_color,
>     +                       .use_clear_address = use_clear_address,
>                             .write_disables = write_disable_mask);
> 
>         blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
>     @@ -1300,9 +1304,11 @@ blorp_emit_surface_state(struct blorp_batch *batch,
>         blorp_flush_range(batch, state, GENX(RENDER_SURFACE_STATE_length) * 4);
> 
>         if (surface->clear_color_addr.buffer) {
>     -#if GEN_GEN > 10
>     -      unreachable("Implement indirect clear support on gen11+");
>     -#elif GEN_GEN >= 7 && GEN_GEN <= 10
>     +#if GEN_GEN >= 10
>     +      assert((surface->clear_color_addr.offset & 0x3f) == 0);
>     +      blorp_surface_reloc(batch, state_offset + isl_dev->ss.clear_value_
>     offset,
> 
> 
> Are the value offset and the address offset the same?  I think they are, but
> just want to be sure. :-)

Yes, they are. I thought about adding a new field like
isl_dev->ss.clear_address_offset to avoid confusion, but they would
end up being the same, so I just reused it. I can change this if you
prefer.

>     +                          surface->clear_color_addr, 0);
>     +#elif GEN_GEN >= 7 && GEN_GEN < 10
>            struct blorp_address dst_addr = blorp_get_surface_base_address
>     (batch);
>            dst_addr.offset += state_offset + isl_dev->ss.clear_value_offset;
>            blorp_emit_memcpy(batch, dst_addr, surface->clear_color_addr,
>     --
>     2.14.3
> 
>     _______________________________________________
>     mesa-dev mailing list
>     mesa-dev@lists.freedesktop.org
>     https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 
>